Importing LEF of analog block to SOC encounter

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savi

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Jan 4, 2010, 7:38:45 AM1/4/10
to IndiaChip
Hi all,
We have imported the lef file of the analog block into SOC Encounter.
But the analog block does not contain all the pins.
Eg: The lef file of inverter consists of 4 pins namely:
out,in,gnda,vdd
But after importing to SOC the analog block has only out, in, gnda.
vdd pin is not obtained.
But we have got all the 4 corresponding ANALOGESD pads.
The log of this displays as follows:

Loading Lef file ../lefs/inv.lef...
**WARN: (SOCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
**WARN: (SOCLF-200): Pin 'gnda' in macro 'inv2' has no
ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'gnda' in macro 'inv2' has no
ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'out' in macro 'inv2' has no
ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'out' in macro 'inv2' has no
ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'in' in macro 'inv2' has no
ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.


Thanks
With regards
savitha

VNIT

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Jan 4, 2010, 7:57:10 AM1/4/10
to indi...@googlegroups.com
Hi,
I think you can safely ignore the above warnings and proceed with integration.
--
With regards,

VLSI Design and Research Lab,
VNIT, Nagpur.
http://ece.vnit.ac.in/vlsi/VLSI_LAB/VDRL.html
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