Fwd: Urgent: Regarding SCL 180nm foundry: problem to run DRC and LVS

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Vishal Sharma

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Jul 17, 2017, 11:19:20 AM7/17/17
to d.she...@gmail.com, mit...@cadence.com, tanmay dubey, Chandra Shekhar Gautam, pinal engineer, anil rawat, npi...@cadence.com, indi...@googlegroups.com, Iliyas malik, chandrashekhar kukade, anand kumar, naveen bishnoi, Pankaj Kumar, sunny sharma, ChArAnPrEeT SiNgH, manish tikyani, manish jaiswal, Santosh Kumar Vishvakarma

Dear All,

I hope you are doing well.

For this moment, I need your help if you can do anyhow
.
Actually, I am trying to run DRC and LVS  for the layout design with the SCL 180nm for SMDP C2SD project and Mentor Graphics' Calibre tool, but finding error. The screenshots are attached.

If anyone of you feel that you can help, then I would give you the access of my PC so that you can exactly check the problem.


--
Thanks & Regards,

VISHAL SHARMA
PhD Research Scholar,
Nanoscale Devices, VLSI Circuit & System Design Lab,
Electrical Engineering,
IIT Indore
+91 9685551573

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chandrashekhar kukade

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Jul 22, 2017, 4:38:52 AM7/22/17
to pinal engineer, Vishal Sharma, manish jaiswal, Mithun Kumar Swain, Santosh Kumar Vishvakarma, manish tikyani, anil rawat, d.she...@gmail.com, anand kumar, naveen bishnoi, sunny sharma, Iliyas malik, Chandra Shekhar Gautam, ChArAnPrEeT SiNgH, npi...@cadence.com, Pankaj Kumar, indi...@googlegroups.com, tanmay dubey
Hi, 

You need merge gds of all cells with your top level gds. 
Then run drc, lvs on merged gds. 

Thanks 
Chandrashekhar 

On Jul 21, 2017 10:45 PM, "pinal engineer" <pinale...@gmail.com> wrote:
Dear all,

Here, we found cell error in DRC. All cells of design are not present in layout. so any one can give the solution how a CALIBRE can read these cells from layout in DRC error check.

Attached snap of DRC error below for scl 180 nm.

Thanks &Regards

--
Pinal Engineer
SVNIT, Surat

On Tue, Jul 18, 2017 at 10:23 AM, anil rawat <anils...@gmail.com> wrote:
Dear Vishal sir

For SCL FDK
1) U need to choose DRC.header under the Rules tab in the calibre and give the path of file "TS18SL_SCL_CALIBRE" in DRC.header from the location where it is present in your system
2) export from layout viewer should be enable.

Same for LVS.header when doing LVS.

We are about to submit two tape-outs to SCL foundary after solving lot of foundary related issues.

regards
anil

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