Need help Regarding .lib and .lef generation for a new standard cell creation

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Vishal Sharma

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Aug 23, 2016, 7:20:55 AM8/23/16

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Dear All,

I am trying to go through the complete ASIC design flow with cadence environment and 180nm. For backend design I am using Encounter tool of cadence. For schematic and simulation, I have virtuoso tool. After the circuit simulation, I can generate gate level nelist only when all the standard cells are available in the technology file. My problem is that, how to create a new standard cell in .lib and .lef file format, if it is not available in technology file, so that I can call it while generating the netlist of my larger system design employing this specific standard cell.

Thanks in advance.

Thanks & Regards,

VISHAL SHARMA

PhD Research Scholar,

Nanoscale Devices, VLSI Circuit & System Design Lab,

Electrical Engineering,

IIT Indore
+91 9685551573

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