Re: Regarding the connection of SCL 180nm I/O Pads

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Iliyas malik

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Feb 9, 2018, 3:58:09 AM2/9/18
to deep shekhar, Mithun Kumar Swain, tanmay dubey, Chandra Shekhar Gautam, pinal engineer, anil rawat, npi...@cadence.com, indi...@googlegroups.com, chandrashekhar kukade, anand kumar, naveen bishnoi, Pankaj Kumar, sunny sharma, ChArAnPrEeT SiNgH, manish tikyani, manish jaiswal, swapne...@gmail.com, akshay...@gmail.com, a.goy...@gmail.com
Dear all,
  I can not help you regarding these methodology type issue. But i am available to help you people at circuit level particularly analog circuits. 


reagards:
iliyas

On Thu, Feb 8, 2018 at 3:48 PM, deep shekhar <d.she...@gmail.com> wrote:
Hi all,

This is Deep Shekhar from NIT Jalandhar.

Has anyone completed the design for tapeout using SCL 180nm Analog IO pads. I am not able to understand exactly which pads are to be chosen for 1.8V VDD.

If anyone has completed, it is requested that kindly give the proper steps so that we could proceed further. we are stuck at this point.


Thanks and Regards
Deep Shekhar
Project Faculty (SMDP-C2SD)
Department of Electronics & Communication Engineering
Dr B R Ambedkar National Institute of Technology (NITJ)
Jalandhar - 144 011 (Pb)
+91-9463523312



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With regards
Mohd Iliyas
Mo. No. 09465829393

Vishal Sharma

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Feb 9, 2018, 5:41:36 AM2/9/18
to indi...@googlegroups.com, deep shekhar, mit...@cadence.com, tanmay dubey, Chandra Shekhar Gautam, pinal engineer, anil rawat, npi...@cadence.com, chandrashekhar kukade, anand kumar, naveen bishnoi, Pankaj Kumar, sunny sharma, ChArAnPrEeT SiNgH, manish tikyani, manish jaiswal, Swapneel Bhandarkar, Akshaya Goyal, Arun Goyal
pc3d01 analog input
pc3o01 analog output
Pvdi       core vdd
Pv0i     core VSS
Pvda    pad VDD
Pv0a    pad VSS


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