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What is a referral?
An eligible referral is a friend,
relative or professional acquaintance known to an employee, whose
qualifications
potentially match the requirements for a Synopsys job opening in any
location. Referrals are always subject to the rules of the scheme.
What's in it for you?
For every eligible referral hired, the eligible referring employee will receive a bonus. Jobs which are designated
"Hot Job" will pay a double bonus.
How to submit a referral?
In order to be bonus eligible Synopsys employees must submit a resume using the
Employee Referral Gateway.
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Featured Jobs - Synopsys NCR Bangalore Hyderabad
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Location: - Noida
Keywords: Experience in scripting (Perl/Python/Tcl), Linux shell scripting, Experience in Test Automation, debugging, regression testing C/C++, computer architecture, Understanding of Processors from ARM / Tensilica / IBM, or Peripheral model internals or Interconnects like AXI / AHB, Embedded software |
Job ID & Title: 5750BR, R&D Engineer, Sr. I
Location: - Bangalore
Keywords: C/C++, Data Structure, Algorithms, High Level Synthesis. Job ID & Title: 5350BR, R&D Engineer, Staff
Location: - Bangalore
Keywords: C/C++, Data Structure, Algorithms, FPGA Synthesis, Timing constrains, Static Timing Analysis, TCL. |
Location :- Hyderabad
Keywords : Memory full custom layout design , Physical Design methodologies / Phases , CMOS , Fabrication Methodology
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Job ID & Title: 5682BR, 5114BR & 5719BR Memory Circuit Design Engineer, Sr. I, Sr. II, Manager R&D.
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Job ID & Title: 5798BR,
R&D Engineer, Sr. I (SystemC Modeling)
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Job ID & Title: 4043BR, CAE Sr. I
Location: - Bangalore
Keywords: wide range of IP, from AMBA AHB/AXI components to peripheral components, i.e. I2C, SPI, UART, timers 5years. Understanding of system
design and logic design using an HDL language, synthesis, simulation and
verification EDA tools is important. Occasional travel will be
required.
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Location :- Hyderabad
Keywords:-Analog and mixed signal Layout, CMOS circuits, high speed logic paths, layout techniques (ESD, Latchups). Managing
and growing team exp
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Job ID & Title: 5699BR & 5700BR, Memory Circuit Design Engineer, II
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Job ID & Title: 5572BR,
SoC Platform Design Engineer, Sr. II
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Job ID & Title: 5324BR, CAE, Staff
Location: - Bangalore
Keywords: FPGA based prototyping/emulation of complex SoCs. Good understanding of the issues involved in ASIC to FPGA RTL. FPGA architectures such as Xilinx Virtex 7/Altera Stratix V. Knowledge of ARM buses, display controller/interface, protocols MIPI, HDMI, USB, PCIe, SATA. |
Location :- Hyderabad
Keywords :- Prior experience in managing/leading and growing a team ,
RTL Coding , Verification , System Verilog , OVM Methodology , Protocol knowledge like : PCIe/USB/SATA
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Keywords: experience in
Full/semi-custom memory layout design, Physical Design methodologies,
Floor Planning, Place & Route, Physical Verification, Signal
Integrity, DRC, LVS, CMOS, Fabrication Methodology
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Job ID & Title: 4753BR, Processor Architecture Design Engineer, Sr. II
Keywords: ISA (Processor Instruction
Set Architecture), ADL (Architecture Description Language), C/C++,
SystemC, Pipelining, Caching, Instruction Level Parallelism, ISS
modeling, VLIW, SIMD, Unix
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Job ID & Title: 5849BR, R&D Engineer
Location: - Bangalore
Keywords: Physical Design, ICC, ICV/Hercules. setting up and perform chip level tasks for place & route, static timing analysis using Prime Time, physical verification, layout editing, power analysis and RC extraction. |
Location :- Hyderabad
Keywords :- Prior experience in managing/leading and growing a team ,
RTL Coding , Verification , System Verilog / OVM, Protocol knowledge like:
PCIe/ USB/
SATA
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Job ID & Title: 5630BR, 5744BR, 4834BR & 4835BR, Full Custom Memory Layout Design Engineer II, Sr. II
Keywords: experience in
Full/semi-custom memory layout design, Physical Design methodologies,
Floor Planning, Place & Route, Physical Verification, Signal
Integrity, , DRC, LVS, CMOS, Fabrication Methodology
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Job ID & Title: 4404BR, 4856BR & 5610BR, Verification IP Development Engineer, Sr. II
Location: - Delhi/Noida
Keywords: Verilog, System Verilog, OVM/UVM/VMM, Protocol knowledge (AMBA/AHB/AXI/USB/PCIe/Ethernet /SATA/MIPI/HDMI), Emulation, Zebu/Palladium platforms, Synthesizable VIPs, Transactor (Xactors), DDR SDRAM |
Job ID & Title: 4660BR, Field Apps Engineer (DDR SDRAM)
Location: - Bangalore
Keywords: DDR3, DDR4, LPDDR2 or LPDDR3 SystemVerilog TestBench, or high level verification methodologies e.g. UVM, VMM or OVM, Synthesis & Timing |
Job ID & Title: 5088 BR , R&D Engineer, Sr I
Location :- Hyderabad
Keywords: Transistor level circuit design, SERDES subs circuit exp. (i.e. TX, RX ,adaptive Equalizers-(FIR, DFE, CTLE), PLL/
DLL/BGR, Regulators) (jitter, amplitude, noise)Tools:
HSPICE/ FINESIM
/ MATLAB
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Keywords: VHDL RTL model, Verilog
Behavioral model, Liberty Timing model, Verilog Techbench, DFT views
like Tetramax & Fastscan, Ekos Emulation model, TCL/Shell/Perl,
understanding of EDA views and flows.
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Job ID & Title: 5626BR, EDA Tool Development Engineer, Staff
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Job ID & Title: 5269BR, Physical Design Specialist (Apps Consultant)
Location: - Bangalore
Keywords: Physical Design. ICC Experience, Place & Route. |
Job ID & Title: 5697 / 5698 BR / 5701/5702/5703/5704 BR , R&D Engineer, Sr II / R&D Engineer II
Location :- Hyderabad
Keywords: SRAM, ROM, Memory
compiler, memory circuit design, CMOS, DRC, LVS, Parasitic extraction,
Bit Cell Analysis, Architecture, Characterization, FINFET
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Job ID & Title: 5510BR, CAD Engineer
Keywords: Good knowledge of UNIX, Familiar with EDA tools and flows, knowledge of PDK development/verification/circuit simulation, knowledge of scripting languages like Perl/Tcl/Shell.
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Job ID & Title: Multiple reqs (R&D Engineer, Sr.I, Sr. II, Staff, Sr. Staff) for Emulation
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Job ID & Title: 4706BR, Verification Specialist (Apps Consultant)
Location: - Bangalore
Keywords: System Verilog, OVM/UVM, Protocols: PCIe/AMBA AXI etc. |
Job ID & Title: 5461 BR , Application Engineer Sr I
Location :- Hyderabad
Keywords :- Design Compiler , Prime time , Formality
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Job ID & Title: 5153BR, Sr. Program Manager
Location: - South Korea
Keywords: Understanding of semiconductor design flow Experience of design (library or IP
or SOC) & silicon validation, Experience in interface IP protocol
(USB, DDR, MIPI, HDMI etc), Experience of program management. (Schedule,
Resource, Contract management
etc)
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Job ID & Title: 5745BR, Field Apps Engineer (Logic Library)
Location: - Bangalore
Keywords: Physical Design, Place and Route, Timing signoff, Synthesis, Extraction, and LVS/DRC. |
Job ID & Title: 5018BR, Design Consultant (Physical Design)
Location: - Bangalore
ASIC designs at chip level and block level
Debugging skills.
Proficient in HVL (System Verilog)
and Methodology (UVM preferred). OOPs concepts, Verilog, Scripting
skills. Experience in at least 2 protocols - AMBA, PCIe, USB, MIPI,
Ethernet – will
be a plus..
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Job ID & Title: 4786 BR , CAE Sr I
Location :- Hyderabad
Keywords PDK and overall design flow , knowledge of scripting languages like Python, Tcl or other EDA extension languages
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Senior Physical Design Specialists
7-9 years. 3 positions.
Location: South Korea
Place n Route, CTS, Good ICC Experience.
Design experience of 22nm/28nm
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Job ID & Title: 5496BR, R&D Engineer I
Location: - Mumbai
Keywords: Test Planning, Test Specification dev, documentation & execution of tests in compliance with IEEE standards, Automated testing tools Scripting expertise in VB or Perl, Testing of database & backend components, QA Partner, Rational Test Studio, Implementation of SQA techniques |
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