| Editor's Note |
| Chip designers who think there are already too many design rules placing restrictions on creativity have not seen anything yet, according to a researcher at IBM's Austin Research Lab. In a paper presentation earlier this month at the International Symposium on Physical Design, Kevin Nowka predicted that the number of design rules would growth exponentially beyond the 22-nm node.
Designers know all too well that the difficulties associated with design-for-manufacturing won't get any less pronounced as time goes by. Shoehorning designs with smaller and smaller linewidths into manufacturing processes will only get more challenging.
In the past some have balked about the area penalty and design constraints prescribed by restrictive design rules (RDRs). But according to prominent EDA analyst Gary Smith, principal of Gary Smith EDA, RDRs "are not as restrictive as some engineers would make you believe. At worst they look like the old fix height standard cells that VLSI Technology used to sell. At best, they clean up a lot of bad practices that we've fallen into at layout."
In any case, the question for the industry now appears to be not whether designers can afford to accept the tradeoffs mandated by RDRs, but whether they can afford not to.
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| Top Story |
IBM warns of 'design rule explosion' beyond 22-nm
The recent The International Symposium on Physical Design featured a warning from IBM about "design rule explosion," Mentor Graphics' pitch to the automotive sector and a proposal from a former Cadence Design Systems Fellow on using EDA to study the human brain.
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| Semiconductor News |
Analyst: Spansion's EcoRAM 'nearly dead'
At one time, Spansion Inc. was touting its green memory line as a replacement for DRAMs in servers.
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Enlarged Renesas climbs the chip vendor ranks
The carefully prepared merger transaction of NEC Electronics Corp. and Renesas Technology Corp. has been completed to create Renesas Electronics Corp., the world's third (or fourth) largest chip company.
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Micron beats Street, sees NAND fab ramp
Micron Technology Inc. beat Wall Street's estimates amid an ongoing recovery in the memory market.
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| Commentary |
Join the Conversation: Is Silicon Valley losing its mojo?
Recent reports suggest Silicon Valley is slipping as a place to find a good job. What's happening from where you sit as an employer, employee or job seeker?
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Comment: Scaling, collaboration are keys to maintaining U.S. cleantech edge
Scaling existing technologies and collaboration among industry, gvernment and universities is the best way for the U.S. to maintain its edge in clean-energy technology.
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| Business News |
Analog Q1 preview: What analysts are saying
There are still select shortages and extended lead times in the analog arena. And demand looks strong--at least until the third quarter.
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IC shortages seen, but inventories grow
The IC industry is recovering, but there are also signs of growing chip inventories in the channels.
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AMD gained MPU share in Q409, says iSuppli
AMD increased its share of the global microprocessor market to 12.1 percent in the fourth quarter of 2009, as the company took share from both larger rival Intel and smaller players, according to market research firm iSuppli.
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Global OLED revenue jumped 35% in 2009, says analyst
Revenue for orgamic light emitting diode displays jumped 35 percent in 2009 to $826 million, according to market research company DisplaySearch.
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Applied's analyst party: What experts are saying
Applied Materials Inc. held its analyst event. Here's what observers said about Applied and its efforts in fab tools, solar and its ongoing shift to Asia:
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| Design News |
Europe backs thermally-aware EDA project
Europe's big three chip makers — STMicroelectronics, Infineon Technologies and NXP — are all taking part in a three-year European collaborative research project to try and improve thermal-awareness and thermal effect modeling within IC design.
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RTL synthesis can accelerate the entire implementation flow
You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SoC). With just a few weeks remaining for final synthesis, place and route (P&R) and post-layout verification tasks, you wonder: can I still finish the job on schedule?
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PrimeSense confirms Microsoft 'Natal' design win
PrimeSense Ltd. (Tel Aviv, Israel) a developer of a 3-D recognition sensor technology, has said it is providing the 3-D sensing technology for Project Natal for the Xbox 360 from Microsoft.
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| ESC Silicon Valley |
ESC: The results are in for embedded engineering survey
The 2010 Embedded Market Study is complete and tallied. Big surprises? Yes and no.
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Dylan McGrath is editor of the EE Times Newsletter, which brings you the latest semiconductor and design news.
