Defining the 45 nm Logic Node
oceanwave
Craig Sander, corporate vice president of technical development, AMD,
Sunnyvale, Calif.
Although the most recent International Technology Roadmap for
Semiconductors (ITRS) does not show the 45 nm node going into
production until 2010, each company will have its own set of design
rules, and it is a vast simplification to expect that a node can be
described by the small number of pitches and areas provided in the
ITRS. Also, the ITRS has traditionally defined the node dates based on
expectation for DRAMs - not logic. What you can expect for most logic
ICs is that the 65 nm rule set (for each company) will provide a linear
shrink relative to 90 nm of about 0.7, leading to a density increase of
about 2×. (Take a block of logic implemented in transistors and
interconnect and shrink it by a factor of 0.7 in each direction and the
area will be about half of what it was in the previous generation.)
This 0.7 linear shrink for each successive generation has characterized
the logic IC industry for some time: 90/130=0.69, 65/90=0.72, and
45/65= 0.69. This is how the industry decided to pick "45 nm" rather
than say "50 nm" as the name that is most typically used to describe
the next node.
I would define 45 nm technology as a technology that will shrink
existing 65 nm design rules by a factor very close to 0.7. And yes,
this does mean that one company's "45 nm" technology will be different
from another's.
However, at 45 nm, things could get a bit more interesting. It is
possible, maybe even likely, that the companies that are first to
introduce "45 nm" technology will actually ship products with a linear
shrink factor that is greater than the traditional 0.7. This is because
the industry is running into real limitations with the currently
available lithography tools. The key to truly manufacturable "45 nm"
technology will be high-NA (NA=1.2) 193 nm immersion scanners, and they
are not going to be available as soon as the industry would like. Once
they do become available, it will still take time to hone the processes
that utilize the tools and to get these process implemented into
high-volume manufacturing. Those that are first to introduce the next
node might have to do so with less capable scanners and wind up
shipping something more accurately referred to as "50 nm" or maybe "52
nm" technology.
Fred Chen
Presumably if the same scanners are used for "90 nm" and "65 nm"
critical layers, it is expected the same reuse strategy would be used
for "45 nm" and "32 nm".