Interview Questions

[Sven Meier]

Hi Everyone,

Could everyone help me out with the following questions I would like to be able to answer on the spot for interviews?  I don't want exact numbers under precise conditions you know from projects as that should not be discussed if not presented publicly, but more round numbers and ranges representative of 22nm technology in general.  For example 3.4 is "less than 5ps"  These are sort of ballpark numbers.

I'll set up a meeting this week where we can practice and discuss.

-Sven

What is the typical gate delay of a 2 input nand?  What is its size and input cap load?

What are the fastest and typical ASIC frequencies in 22nm (or 32nm)?   (We know from previous designs, custom processors max at a little over 5Ghz)

How many gate delays are in a cycle?  For a common 3.5 GHz (ex. x86) machine?

What is the clock skew on a large ASIC design (clock tree)?  Local (close to same leaf of tree)?  Global (anywhere within cycle reach)?

What is the clock skew on a large custom processor (grid design)?   Local (adjacent latch bank)?  Global (anywhere within cycle reach)?

How many picoseconds is PLL jitter?  How many picoseconds is supply noise jitter?

What is a typical setup, hold time and CLK-to-output delays for a latch?

What is a typical metal pitch for fine metal?  What about contacted pitch?  What about contact to diffusion pitch?  What percent of a wiring level is taken up by power?

-Sven

Some questions we could go over in a meeting: 

What are the tradeoffs between a clock tree and a clock grid?

[Matthew Newman]

For those in california for apple today tomorrow....my number is 5082437675. I'm staying at the cypress tonight...if people are in early and want to grab food....call me...I should be in cupertino by 6

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