Fwd: Referrals
Brian Jones
From: Jeff West <je...@tss-consulting.com>
Date: Sat, Jun 29, 2013 at 1:13 PM
Subject: Referrals
To: brian....@gmail.com
Hi Brian,
Can you send me the names / contacts of any Digital Verification Engineers you know or were affected by the IBM lay offs? I have 8 positions open (varying levels of experience ). Sample for principal below.
Your help would be greatly appreciated.
Personnel in the Configurable Digital Logic (CDL) Department develop and verify FPGA designs for all major vendors and device families including: Xilinx, Altera, Lattice, and Microsemi. The Department also designs digital ASICs and performs obsolescence mitigation activities, including redesign, for digital ASICs. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, partition and perform code development, simulation, place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.
The CDL Department is deploying a Unified Verification Methodology (UVM) based verification capability and is seeking a senior verification engineer to lead all aspects of development, deployment and execution of the Department's verification strategy. Responsibilities include, but are not limited to:
* Participating in the functional verification of ASICs/FPGAs as-needed
* Leading and mentoring teams of verification engineers
* Creating the verification plan with the Program and RTL designers input and review.
* Developing the architecture and design of the environment as well as participating and/or leading a team of engineers to implement the test benches.
* Creating the necessary run and/or post-processing scripts as well as the overall methodology for the given project in terms of the logistics related to using the verification environment
* Implementation of the verification environment, including:
* Creation of Constrained Random Agents
* Creation of Monitors and Scoreboards
* Incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models
* Creation of functional coverage through use of assertions, etc.
* Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan.
* Writing directed and constrained random tests in parallel with RTL designers to help achieve coverage goals.
* Use of trouble reports and bug tracking
Required Skills for Principal Electrical Engineer:
Minimum 10 years FPGA/ASIC verification experience is required.
Demonstrated experience and expertise in the following areas is required:
* Creation of verification plans
* Implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage
* Experience leading a verification team and able to interface to the RTL designer and program/customer as-needed
* Proficient in SystemVerilog
* Experience with one or more of the following: UVM, OVM, eRM, VMM
* Proficient in C/C++.
* Proficient in scripting languages and utilities including Make, Perl, Python, Tcl and Shell scripting
* Experience with Questa/Modelsim (preferred), VCS and NCsim (acceptable).
* Development and execution of verification process improvement plans
* Team leadership
* Development and deployment of verification strategies and methodologies across teams and organizations
* FPGA/ASIC design and verification using a Linux based development environment
* Creation of plans, schedules and cost estimates for design verification efforts
Candidates must have broad experience and be expert in the design of FPGAs. Must have written VHDL, simulated, synthesized, placed and routed, integrated and tested FPGA/ASIC designs on hardware. Expert level knowledge of simulation tools such as Questa or Incisive, synthesis tools such as Synplify, and back-end tools such as Xilinx ISE, Altera Quartus, or other FPGA vendor tools is required. Candidates must have an understanding and appreciation of technical themes and concepts and the ability to develop solutions independently, but also be able to work with systems engineers, software teams and peers to define requirements.
Demonstrated experience and success in applying best in class design methodologies and tools is required. Working knowledge of Microsoft Office products required. Candidates must be highly motivated, high performers with excellent verbal and written communication skills and a strong desire to learn and contribute in a fast-paced team environment. Demonstrated leadership skills with a demonstrated ability to lead a design verification team is required. Experience working in a distributed design and development environment, including tools and methodologies is required. Strong communication and interpersonal skills required.
At a minimum an Interim Secret clearance will be required to start.
Desired Qualifications:
* UVM testbench implementation knowledge/experience
* Experience verifying processor-based systems with the use of application code in a simulation environment
* SystemC experience
* MATLAB experience
* Verification in a DOD-Aerospace environment
* Hardware design background
The ideal candidate will possesses several years of RTL design
experience and has more recently been involved exclusively in design
verification. This candidate will be an exceptional leader and experienced
professional who knows how to negotiate trade-offs with customers while
maintaining product integrity. The candidate will pursue a disciplined approach
to ASIC and FPGA design including attention-to-detail and good documentation.
Required Education:
Bachelor of Science in Electrical Engineering
Desired Education:
Master of Science in Electrical Engineering
Best Regards,
Jeff
============================================================
Jeff
West
Managing Partner, East
Coast e-mail: mailto:je...@tss-consulting.com
TSS CONSULTING, LTD.
Visit: http://www.tss-consulting.com/
(781) 269-1852 - Office
(781) 956-9913 - Mobile
Specializing in the recruitment
of Analog/Mixed-Signal, Power Management & RF/Microwave Electrical
Engineers since 1985
LinkedIn Profile: http://www.linkedin.com/pub/jeff-west/0/b5a/890
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matt.newman78
Best Regards,
Jeff============================================================
Jeff West
Managing Partner, East Coast e-mail: mailt...@tss-consulting.com
Joe Schmittlein
Joe
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