Need help with hls4ml ip

[Saxena, Shefali]

Hi,

This is Shefali from Argonne National Lab. I am interested in developing machine learning algorithms in FPGA. I have gone through the tutorial hls4ml-tutorial. I would like to know where the ip is created after hls_model.build step. I cannot find it in impl. directory.

Also, after ip creation, how can I take it to Vivado, generate a bit file, and use the bit file to run ML algo on FPGA? Is there a link to tutorial or steps to do this? I will really appreciate if you can help me with the steps.

Thanks,

Shefali

[Nhan V Tran]

Hi Shefali

Thanks for your interest! 

To export the IP, you can turn on this flag here:

https://github.com/fastmachinelearning/hls4ml/blob/master/hls4ml/templates/vivado/build_prj.tcl#L10

which exports the IP here:

https://github.com/fastmachinelearning/hls4ml/blob/master/hls4ml/templates/vivado/build_prj.tcl#L113-L119

From the command line this would be:

`vivado_hls -f build_prj.tcl export=1`

From the python API:

`hls_model.build(export=True)`

See https://fastmachinelearning.org/hls4ml/autodoc/hls4ml.model.html for more.  

---

After IP creation, integration really depends on the detail of your system.  Is it a Xilinx FPGA?  We have some examples of standalone devkit examples for testing, but again, depends on your setup.  If you don’t mind sharing, we may be able to give more details.

Best

Nhan

On Jun 5, 2021, at 10:35 AM, 'Saxena, Shefali' via hls4ml help <hls4m...@googlegroups.com> wrote:

Hi,

This is Shefali from Argonne National Lab. I am interested in developing machine learning algorithms in FPGA. I have gone through the tutorial hls4ml-tutorial. I would like to know where the ip is created after hls_model.build step. I cannot find it in impl. directory.

<image.png>

Also, after ip creation, how can I take it to Vivado, generate a bit file, and use the bit file to run ML algo on FPGA? Is there a link to tutorial or steps to do this? I will really appreciate if you can help me with the steps.

Thanks,

Shefali

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[Saxena, Shefali]

Hi Nahn,

Thank you for getting back to me. I was able to export the ip:

Yes, I am planning to use Xilinx FPGA either zcu111 or zcu104.

 I am wondering if the input and output can be axis interface and then I can use dma to load the input data and take the data out using jupyter notebooks. If you have an example of Vivado project for data transfer and example jupyter notebooks to load the data and run the ML inference on Xilinx FPGA, which you can share, that would be great.

Thanks,

Shefali

---

From: Nhan V Tran <nt...@fnal.gov>
Sent: Tuesday, June 8, 2021 2:12 PM
To: Saxena, Shefali <ssa...@anl.gov>
Cc: hls4m...@gmail.com <hls4m...@gmail.com>; hls4m...@googlegroups.com <hls4m...@googlegroups.com>
Subject: Re: [hls4ml.help] Need help with hls4ml ip

 

[Nhan V Tran]

Hi Shefali

Great! We have a few examples with AXI interface.  We are actually planning to make these public early next week (bare metal based).  Would that be okay?  For a Pynq-based platform, examples of that exist too, we can work to provide some code for you.

Best

Nhan

On Jun 8, 2021, at 2:41 PM, Saxena, Shefali <ssa...@anl.gov> wrote:

Hi Nahn,

Thank you for getting back to me. I was able to export the ip:

<image.png>

[Saxena, Shefali]

Hi Nhan,

AXI interface and PYNQ based examples would be a great. Yes, I can wait until next week. Please let me know whenever the examples are available. Thanks a lot!

Thanks,

Shefali

---

From: Nhan V Tran <nt...@fnal.gov>

Sent: Tuesday, June 8, 2021 10:59 PM

[Nhan V Tran]

Hi Shefali

Recent results and code are now available from our recent MLPerf Tiny submission here:

https://github.com/mlcommons/tiny_results_v0.5/tree/main/open/hls4ml

We are working to integrate this code into the main code base, but in the meantime, you can see here a full project with AXI interface examples.  Let us know if you have any questions. 

Best

Nhan

[Saxena, Shefali]

Hi Nahn,

Thanks a lot for the link. I have a pynq-z1 board, I will give it a try and will let you know if I have questions.

Regards,

Shefali

---

From: Nhan V Tran <nt...@fnal.gov>

Sent: Thursday, June 17, 2021 9:33 AM

[Saxena, Shefali]

Hi Nahn,

I have tried the example with the pynq-z1 board, have modified the board specifications and successfully generated the bit file.

I got stuck at the "Run test harness software in SDK" step. It gives me the following error:

Can someone help me with this?

Thanks,

Shefali

---

From: Saxena, Shefali <ssa...@anl.gov>
Sent: Thursday, June 17, 2021 9:46 AM
To: Nhan V Tran <nt...@fnal.gov>

[Nhan V Tran]

Hi Shefali 

Wonderful, thanks for having a look.  While the test harness is part of the recipe, it’s not essential (and somewhat challenging to integrate) into the workflow.  It was needed for our MLCommons Tiny submission.  Primarily I was passing this to you as a starting point so you can see how the interfaces are setup in the project since you were asking about that.  Unless you’re particularly interested in the MLCommons Tiny submission (I’m assuming no, let me know otherwise!), I don’t think we should debug the test harness

I’m cc’ing Ben, Giuseppe, and Nicolo now who can help you run the full example.  You have a couple of options either running bare metal or with the Pynq software stack.  If you don’t have any preferences maybe I suggest the bare metal implementation?  If so, they can help get you up and running!

Best

Nhan

On Jul 2, 2021, at 4:01 PM, Saxena, Shefali <ssa...@anl.gov> wrote:

Hi Nahn,

I have tried the example with the pynq-z1 board, have modified the board specifications and successfully generated the bit file.

I got stuck at the "Run test harness software in SDK" step. It gives me the following error:

<image.png>

[Zakria Nabi]

Hi hls4ml Team,

I see that this is an old email chain from a while ago however I felt that it would be great to have a follow-up to this thread. I'm trying to follow the provided link to the GitHub repo that shows an example of getting an hls4ml IP running in Vivado with an AXI Interface. I am using a Xilinx Nexys 4 DDR board which does use the same board part as the Artya 7100t. The issue is the repo shows hls4ml using a backend called 'Pynq' which does not exist anymore in HLS4ML. Additionally, is it possible to implement the AXI Interface for a board such as the Nexys DDR which does not use Pynq (it uses a Microblaze)?

Best regards,

Zakria