Hello List,
There was a long holiday weekend here and I had some large blocks of time to get some things done. I've updated the RTL on github. The main change is to add support for the BeMicro CV with RMII (WaveShare) ethernet. There is now a single parameterized hermes_lite_core.v that is used for both the SDK and CV. Quartus revisions are used and you will find builds for 09SDK 12SDK and 12CV corresponding to the Hermes-Lite version and FPGA board. Any variants (1.0 or 1.1) should just make a copy of the closest revision within Quartus, exit Quartus and edit the corresponding .qsf file.
My second v1.2 board is now working again. I think that my technique of tinning the pads and then soldering on the component leaves the component too high off the board and susceptible to solder joint cracking/breaking. I reheated the some of the solder joints and now it is working. This is the board ZelPro fixed for me and it looks very good.
I tested v1.2 RX with a 73.728 MHz oscillator and found the "noise floor numbers" to be essentially the same as the v0.9 with 73.728. This confirms my suspecion that the ~5 db improvement seen earlier is due to DSP changes in the FPGA when using a 61.44 MHz clock. Perhaps ~1 db of this is from the lower clock frequency to the AD9866 as indicated by the AD9866 datasheet. I was surprised at how well the numbers between the 0.9 and 1.2 agreed. They were never more than 1 dB different, and this was with different frontends, etc. I'm also surprised that pouring copper ground planes to fill in the top and bottom didn't make much different. If I had to give one version the edge, it would be the v1.2.
My next step is to make a handful of minor changes to 1.2 and then send it out to have 50 boards fabricated. I hope to set up the kitting process with my son over the Christmas holidays.
73,
Steve
KF7O