Russian DDC/DUC Work
Steve Haynal
My radio (named Stork) now exists in a few versions. Photo with front panel inside of paper box (and wrong abbreviations of functions) coming not from me.
Following text – is a slightly edited Google translation result.
I present the design of the transceiver operating on the principle of DUC / DDC (digital up-conversion / digital down conversion), receivers with such a structure have a name yet, "the ADC to the antenna."
It is a standalone device that does not require connection to their work with a personal computer. All processing at the reception and the formation of the transmission signal is a signal processor ST STM32F746 in conjunction with the processing of on-chip programmable logic (FPGA) ALTERA CYCLONE IV EP4CE22E22I7N.
The signal path is similar to that used in radio transceiver Hermes, complemented by a two-piece attenuator relay (0/6/12/18 dB) and eight band filter. Band Filter 0..1.6 MHz relay switches, switching a high-frequency filters are PIN diodes BAP64 with a current of 20 mA.
After the filter the signal passes LTC6401-20 UHF and enters the ADC LTC2217 (or LTC2208), data on 16-bit bus arrive in FPGA. The clock ABLNO 122.880MHz with its low noise power supply. CMOS signal at 122.88 MHz is supplied to the ADC is distributed (in the form of differential signals through a driver TI SN65LVDS1DBV, FPGA and DAC transmitter.
On the transmission signal is generated 14-bit DAC AD AD9744ARUZ and after amplification in the two-stage amplifier on chips TI OPA2674I-14D (up to +26 dBm maximum power) is supplied to the final stage of the push-pull transistors ST PD55008-E.
In the FPGA structure is formed from the quadrature mixer, decimator (R = 2560, N = 8, D = 1) and the FIR filter 1441 of the second order with coefficients reload themselves. At the inlet and outlet of the filter used 32-bit values of the quadrature signals. The filter is also used when forming the transmission signal, the output signal is fed to an interpolator (R = 2560, N = 5, D = 1) and the quadrature mixer.
Processor Communication and FPGA to transmit I/Q signals is carried out according to the protocol I2S (in processors from ST it provides peripheral controller SAI - Serial Audio Interface) with a total length of a frame of 256 bits - which allows the reception to pass more than one pair of quadrature signals (2 * 32 bits) . Using a multi-channel decimator blocks and two separate FIR filters offers two independent channels of reception in the FPGA.
Once filtered by the frequency data quadrature channels transmitted to the processor over them scaling is to provide the required characteristics of the AGC (time - with the "fast" and "slow" channels and amplitude - 10 dB increment of 1 dB input increment output) .
The demodulated signal (as well as the transfer of self-control signals telegraph, voice keystrokes, etc.) in the form of 16-bit samples at a frequency of 48 kHz is supplied to the codec NUVOTON NAU8822LYG, which are connected to the headphones and microphone operator. In addition, to the bridge connecting the speaker output of the codec up to 1 watt. Just use the built-in capabilities of the codec DSP equalizer to process the signal from the microphone.
To power the digital part and the small-signal transceiver circuit board mounted on the pulse converter with an output voltage of 5 volts. On the advice of Makarkin Sergey RX3AKT applied chip TI LMZ35003RKG. The inverter, it operates at a frequency of about 485 kHz, the local screening of the inverter even without additional screen minimizes interference with reception.
for "secondary" consumption voltage (5 volts) transceiver while taking about one ampere. Thanks to the inverter power of 12 volts while consuming about 650 mA.
The preliminary stages of the power amplifier (2 * TI OPA2674I-14D) when receiving transferred to the low-power mode. Power stages provide linear regulator (ST LDFMPT) with an output voltage of about 11.2 volts.
The offset to the gates of the output transistors (2 * ST PD55008-E) is determined by the trimmer. The current consumed by this cascade is controlled by a Hall effect sensor Allegro ACS712ELCTR-05B-T.
Construction - four-layer printed circuit board, one of inner layers - the land is used for screening and provides heat dissipation from the ADC and the final stage of the power amplifier.
The project design and manufacture of business advice or help:
RA1AGB, RK1AQ, RA1AGO, UA1ADT, RX9CIM, RX3AKT, RA9MMQ as well as a lot of people.
Steve Haynal
Steve Haynal
My be you see before…
http://rus-sdr.ru/visair/ - only commercial sdr radio user interface controller, also connected to dsp board http://rus-sdr.ru/modul-dsp-v2-0/ and to HIQSDR-Lite,
In DSP (STM32F7xx) utilized frequency-domain 48/96 kHz IQ signal processing (not filtered, for spectrum display functionality).