Hermes-Lite 2.0 - Invitation to view

[Steve Haynal (via Google Drive)]

Steve Haynal has invited you to view the following shared folder:

Hermes-Lite 2.0

Start of Hermes-Lite V2 BOM

Open

Google Drive: Have all your files within reach from any device.

[f1v...@orange.fr]

Hi Steve.

What can I say.

The only way now is onwards and upwards.

A start to greater things.

73 Peter F1VKK

[Steve Haynal]

Hi List,

The Clock schematic and BOM sheets are now in the Google drive linked in this thread. The Ethernet schematic has been updated.

73,

Steve

KF7O

[James Ahlstrom]

I ran into a small issue when trying to substitute an 80 MHz clock on the V1 board.  Most 4-pin oscillators have an enable pin, but some require Vcc while others require Gnd to turn them on.  Of course my 80 MHz unit needed the wrong polarity.  Most oscillators will turn on if the enable pin is left open.  So leaving the enable pin open is a general solution.

Jim

N2ADR

[Steve Haynal]

Hi List,

The schematic and BOM page for the portion of the V2 RF Frontend that is complete is now on google drive. This is just the AD9866 and FPGA connections as the analog portion for TX and RX have yet to be determined. Note that the FPGA pins are place holders for high speed, low speed or clock capable pins, and the actual assignments will be made during layout. For anyone interested in the development Kicad files, there is now a version 2 branch on github. The planned next steps are:

1. Complete power supply schematic and BOM page which also includes FPGA power pin connections and rest of FPGA device
2. Complete Input/Output schematic and BOM page. This includes 2 repurposed stereo jacks for external switches, 4 to 8 position dip switch, bank of 8 LEDs, driver and connector for filter switching, 2 optional SATA connectors for daisy chaining Hermes-Lites, optional SMA jack for external frequency reference, small connector (4-8 signals) for additional communication with PA/filter board, byteblaster connector. The power connector, ethernet connector, and RF connectors are on other schematics. 
3. Create footprints for all components.
4. Layout everything but the RF analog portion on 10cm by 8cm board, reserving as much space as possible for the RF analog portion. Two enclosures for the tall sandwich configuration as specified on the V2 wiki have been ordered.
5. Once the space for the RF analog portion is determined, test and finalize what can be used there, building off of the experiments by others already under way.
6. Finish schematic and layout for RF analog portion, and come to final agreement on connector placement for companion filter/PA card.
7. Order a few boards, build and start the bring-up testing!

73,

Steve

KF7O

[Steve Haynal]

Hi List,

I have added the power schematic to google drive. This also includes the FPGA's power connections. The BOM on google drive has been updated. Github has the latest kicad files under the v2.0 branch.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

The Hermes-Lite V2 schematics now include the input output page. Except for the RF analog portion which will be defined after ongoing tests, this completes the rough schematics and BOM for Hermes-Lite V2. There are most likely mistakes, rough/unclear portions and places for improvements, so now is a good time to take a close look and provide feedback. You can find the schematics and latest BOM (both google sheets and PDF version) on google drive. You can also find the latest KiCAD files, including PDF versions of the full schematic and bom on github. Finally, the latest full schematic and BOM are attached as PDFs to this post.

I must take a short break to complete my taxes, but the next step is to create required footprints for PCB layout.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

I finished the footprints for the 5 largest ICs this weekend. They are on github. After some changes from what I've done in the past, I hope these footprints, including the AD9866 footprint, now do a better job for any solder stencils. I'd like to finish all the footprints in the next week or two, and then move on to floorplanning. I haven't received any feedback yet on the schematics. The earlier I receive worthwhile feedback before things firm up more, the better chance there is I can incorporate it.

73,

Steve

KF7O

[Alan Hopper]

Steve,

can any of the planned connectors be used as a simple serial interface? This would allow easy remote control of external accessories based on  simple microcontrollers.

73 Alan M6NNB

[Steve Haynal]

Hi Alan,

Yes, the JTAG connector, CN7, is my first choice for serial communication. There is a nice JTAG IP block for the Altera parts and good opensource JTAG libraries for microcontrollers, SBC, etc. We use this method for a product at work and achieve ~30 Mb/s, enough for even 1 or 2 receivers. Also, one of the SATA connectors, CN9 or CN10, can be repurposed for simple serial protocol. Finally, pins on the connector to the companion card, CN8, can be used for simple serial protocols. Originally I had planned to dual-purpose some of the slow signals to the ethernet PHY as a SPI, but decided against that given the JTAG must be there and for simplification.

73,

Steve

KF7O

[John Laur]

Hi, Steve,

Has there been discussion of additional input protections on the
CW/PTT lines on this list or was it perhaps another one? I know we
discussed protecting the outputs which are intended to drive relays.

I am concerned that these connections should be a lot more robust
considering the environment and use case (proximity of RF, long
cables, static discharge through the connectors). At the very least
perhaps consider some clamping diodes and a capacitor? I'm sure that
others will have better input on this than me. The Hermes (and
Angelia/Orion) use a 74LC541 buffer not unlike the ULN2803 you are
using on the relay outputs. I have applied quite some abuse to mine
and followed the mailing list quite intently and I have not heard of a
report of anything killing the FPGA pins through it. Is there a 12
channel buffer chip that would serve both CN11 and PTT/CW protection
functions cost effectively? This would give the option to use the
"spare switch input" as a buffered PTT out or something if so desired
and consume barely any extra board space...

I am delighted to see the expanded options on clocking.

I didn't follow the discussion about having unfused power output to
the companion card; that just seems like a good way to bypass a fuse.
I'm not sure that's such a big deal in a small dc system, nonetheless
it seems strange.

73, John K5IT

> --
> You received this message because you are subscribed to the Google Groups
> "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to hermes-lite...@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

[Steve Haynal]

Hi John,

Thanks for the feedback. For input protection on the CN5 and CN6 inputs, the resistors R40,R41,R42 and R43 limit current and are a commonly recommended way to protect FPGA inputs. Currently they are 330 Ohms so as to have 1 BOM line shared with the LED resistors, but this value may increase slightly. Also, the FPGA pins have built-in clamp diodes that will be enabled for those pins. If there is enough room during layout, I will consider adding ferrite beads in series to the resistors to provide some RF isolation. I don't want to add another active component as I think it is overkill. The ULN2803 is necessary on the filter select/PTT outputs as the currents and voltage swings required by the relays are more than the FPGA can handle.

The reasoning behind both CN3 and CN4 is flexibility. Both may not be stuffed. Since a PA companion card may draw more current than the Hermes-Lite, I think it may provide the power to the Hermes-Lite. You have these options:

1. External power to PA, passed to Hermes-Lite vite CN3, protected by F1 (this is an inexpensive resettable fuse) and Q1 (for reverse polarity).
2. External power to PA, protection on PA, F1/Q1 not stuffed on Hermes-Lite, power to Hermes-Lite via CN4
3. External power to Hermes-Lite, passed to PA via CN3, protection on both boards
4. External power to Hermes-Lite, protection by upsized F1 and Q1, passed to PA via CN4, no protection on PA

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

I updated github with more footprints for V2.0. I am on track to finish the footprints this week and start floorplanning this weekend. 

73,

Steve

KF7O

On Monday, April 11, 2016 at 9:11:17 PM UTC-7, Steve Haynal wrote:

Hi Group,

[Alan Hopper]

Steve,

are you planning to put components on one or both sides of the pcb this time?

Alan

[Steve Haynal]

Hi Alan,

There will be components on both sides. The side opposite the major ICs will have smaller components like bypass capacitors. I would like to support double-sided assembly flows like small batch assembly and toaster oven where the solder surface tension must hold the small components on the bottom.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

I updated github with the work from this past weekend. This included tweaks to footprints as well as initial floor and wire planning. So far everything is looking good and we should have no problems fitting into the target form factor. I have a placement which should lead to easy routing. The biggest challenge has been edge length for all the connectors. We only have the front and back edges as the sides slide into the enclosure. To make everything accessible, especially when in the sandwich configuration with the PA/filter companion card, we want connectors on or close to the edge. I have a configuration that works, but will need to reduce the dip switch to 2 or 3 on the edge. I actually prefer fewer dip or jumper configurations, as I'd like it to be easy for V2 to live out of the shack. So far we need 1 switch for selecting the FPGA image (the MAX10 supports 2: recovery and regular) and possibly 1 for selecting the ethernet speed. The MAX10 includes internal EEPROM so options such as MAC, fixed IP, etc. will live there.

73,

Steve

KF7O

 

    

On Monday, April 18, 2016 at 10:29:28 PM UTC-7, Steve Haynal wrote:

Hi Group,

[Steve Haynal]

Hi Group,

The floorplan for HL2 is starting to firm up. A screenshot is attached. 

The HL2 can be mounted on standoffs using the 4 holes supporting M3 screws, or it can be slid into an enclosure. There is a keep out zone on the left and right so that the HL2 can slide into an enclosure.

CN2 in the bottom left corner is a dual footprint for the power connector. It supports a barrel connector or a two connection terminal block.

Proceeding around clockwise, the 6-pin CN3 provides power to or from a companion card. It is as close as possible to an edge to facilitate routing on a companion card. Since this connector is for internal connection to/from a companion card, it is not on the front or back edge. This is a standard 0.1 inch spacing connector. This connector is optional and used only if there is a companion card. Note that this connector is on the bottom side. Bottom sides of both the HL2 and companion card abut, with 8.5mm inbetween. 

To the right of CN3 is U7, the switching power regulator IC. The area around U7 will also have other switching power supply components.

Next is CN7. This is the USB Blaster connector for rescue programming of the MAX 10 FPGA. It is a standard connector defined by Altera. Early adopters will use this to program the MAX 10. Eventually there will be a rescue image on the MAX 10 that supports flashing the FPGA over ethernet. At that point, stuffing CN7 will be optional.  

Above CN7 is CN8. This provides 3.3V, GND and 6 signals for companion card use. It is not on the front or back edge as it is only for proper interfacing with a companion card. Since it is for internal use only, the pins are unprotected. An example use is to support the 4 signal SPI interface on John's companion PA/filter card. This connector is optional. Since it mates with the companion card, it is on the bottom side. It is a standard 0.1 inch spacing header.

Continuing around clockwise, there is CN11. This has the 7 relay + 1 PTT driver signals as well as a common and external voltage reference. U6 is the relay driver IC. Again this is a standard 0.1 inch spacing header. It is on the back edge so those using an external PA and filter setup have easy access. It can be stuffed on the component side or the bottom side for interface to a companion card. 

Next is CN1, the ethernet jack. This is placed to ease routing to U2, the ethernet PHY and then to high speed signals on U3, the MAX10 FPGA. 

After this is P2, this supports an edge launch SMA connector and is an optional clock to the Versa 5 IC, U5. This will not be stuffed by default, but is an option for those wishing to use an external synchronized clock. For example, an external clock driver board with eight outputs can synchronize 8 HL2s.

Next are the 3 RF connectors. First TX, then two (unfiltered, filtered) RX connectors. These support edge launch SMA connectors. If only the TX and filtered RX connectors are used and no P2 is present, then edge launch BNC connectors with fatter coax may be used.

Below the RF connectors down to U1, the AD9866, is space for the frontend opamp and filters. The analog portion is opposite from the power connector to reduce flowing currents in this area.

CN9 and CN10 are two SATA connectors. These are repurposed for high-speed serial data transfer between synchronized HL2s. They are optional.

Below the SATA connectors on the bottom side, are 4 right angle LEDs. They are on the bottom due to limited edge space, but will be visible in all configurations.

After CN10 is P1. This is an edge launch SMA connector to provide a reference clock for the MAX10 that adjusts a VCTCXO if present. Those with a good 10 MHz standard can lock their HL2 to this reference clock. This connector is optional and will not be a part of standard builds. P1 and P2 currently support edge launch and right angle SMA connectors. Since a vertical SMA connector is the least expensive and can be used as edge launch, these will be converted to have the same depth as the three other RF connectors.

Following CN10 is CN5 and CN6, the two 3.5 mm jacks for external switch inputs. These support external PTT in and CW. The current footprint is entirely surface mount, and I am looking for a similar through hole footprint to have a dual option here.

Last is SW1. This is a 2 position dip switch. It can be stuffed with the dip switch specified in the BOM, or standard 0,1 inch header for traditional jumpers. The switches will select rescue or normal image, 100 or 1000Mbs ethernet speed. Other options, such as MAC and fixed IP choices will be in the FPGA eeprom.

73,

Steve

KF7O

 

[f6itu]

Hi Steve

Thank you. The external frequency reference is a must, and the synch output is the nicest overkill function I've seen so far. I allready love it :-)

btw, your last "placement" version hasn't been pushed yet on Github (the 3 RF output of the upper edge are not installed etc.). I tried to explain it to my Kicad,without success : Hungry EDA has no ears

73'

Marc f6itu

[John Laur]

Hello, Steve,

This is excellent to finally see, and I know you have thought a lot about it. 

I have two suggestions for your consideration.

1) Consider a dual SATA header instead of separates. They are consuming a lot of board edge for a feature that may not be used very much. They are available with a height of 13mm which roughly matches the height of a magjack; if you have the height budget for ethernet you should be able to use dual sata headers. See something like the SATAB1-PWA-07 as an example.

2) With the space freed by the #1, consider moving the mag jack to the front edge and P1 to the back edge.

73, John K5IT

--

[Glenn P]

Steve,
what type of 3.5mm jacks are you using?  Do you have a digikey etc number for them as they appear to be a footprint that is one of the less common types?
The much more available and possibly cheaper, type are a little wider though i think.

I am asking because a jack type specified, which appears similar, on a project I built here, costs around $12 each!

The more common type is a stereo jack with/without switching contacts. eg http://www.jaycar.com.au/Interconnect/Plugs%2C-Sockets-%26-Adaptors/Phono/3-5mm-Stereo-SWITCHED-PCB-Socket/p/PS0133
Through hole though.

Glenn
vk3pe

[Steve Haynal]

Hi Marc,

I pushed Kicad changes this last weekend. They should be there now.

73,

Steve

KF7O

[Steve Haynal]

Hi John,

The ethernet jack on the front side was my first choice too, but wire planning really wants it on the back. The MAX10 devices have high speed pins (required by the ethernet PHY and AD9866) and clocks only at certain locations. Routing to high speed pins would be very difficult with the ethernet jack on the front. Also, the PHY would not be above or below the FPGA, but to the right or left. This would be a bad use of space and make the routing quite difficuilt. As it is now, the routing should be a breeze. P1 and P2 are located where they are for proximity to the correct pins for ease of routing.

I also considered a dual SATA connector. Since these are optional, they must be easy to add on at a later time. The dual SATA connectors have a footprint that does not allow easy hand soldering. Also, the prices of single connectors were cheaper than a dual connector when I looked. There is enough space for them. I have to make some adjustments to the connections on the AD9866/SATA side of the FPGA to make sure LVDS signals are on the same bank. This will put the sata connectors on the bottom side and the LEDs on the top side. 

73,

Steve

KF7O

[Steve Haynal]

Hi Glen,

The 3.5mm jack I have specified is this one for $0.66 on DigiKey. I chose it for the price and the narrow (10mm) footprint width. I would like to have an dual footprint that support an alternate through hole jack here. The ones I am looking at on DigiKey are 10mm wide and in the $1 to $2 range. Let me know if there is a jack you like that is 10mm wide or less. I think the one you link to is a bit too wide.

Most of the parts have links and prices on the Google Docs BOM. You can find it at the link in this thread.

73,

Steve

KF7O

[Glenn P]

Hi Steve
Ok on digikey part, cost and width. Its a pity its so tight there that a part possibly hard to get in other countries has to be used. Certainly not available here that I can find.   I cant be sure of the stacking space etc available but wonder if the more common, but wider part could be used and the external Ref connector could be fitted on other side maybe?  Many won't use ext ref I would suspect.

But its your call and with limited space I see why its used.

glenn

On Wednesday, May 11, 2016 at 4:22:35 PM UTC+10, Steve Haynal wrote:

Hi Glen,

The 3.5mm jack I have specified is this one for $0.66 on DigiKey. I chose it for the price and the narrow (10mm) footprint width. I would like to have an dual footprint that support an alternate through hole jack here. The ones I am looking at on DigiKey are 10mm wide and in the $1 to $2 range. Let me know if there is a jack you like that is 10mm wide or less. I think the one you link to is a bit too wide.

Most of the parts have links and prices on the Google Docs BOM. You can find it at the link in this thread.

73,

Steve

KF7O

 

On Tuesday, May 10, 2016 at 9:38:04 PM UTC-7, Glenn P wrote:

Steve,
what type of 3.5mm jacks are you using?  Do you have a digikey etc number for them as they appear to be a footprint that is one of the less common types?
The much more available and possibly cheaper, type are a little wider though i think.

I am asking because a jack type specified, which appears similar, on a project I built here, costs around $12 each!

The more common type is a stereo jack with/without switching contacts. eg http://www.jaycar.com.au/Interconnect/Plugs%2C-Sockets-%26-Adaptors/Phono/3-5mm-Stereo-SWITCHED-PCB-Socket/p/PS0133
Through hole though.

Glenn
vk3pe

[Steve Haynal]

Hi Group,

Attached is the first draft schematic of the V2 frontend. It is largely based on Jim Ahlstrom's tested v1.42 board. Github and Google Drive have also been updated with the latest. Here are a few things to note:

1. Connectors CN4, CN12, CN13, CN14 and CN15 are single inline 0.1 inch spacing headers. They are optional and serve the following purposes:
1. Test points.
2. Connections for frontend bypass board. For example, 6M users/experimenters will need to create their own board and connect it to some/all of these connectors. Experiments with other amps are possible. The frontend bypass board option is on the opposite side from a PA/filter companion card.
3. CN14 is an alternate connection to a PA/filter companion card that will allow RF connectors to remain on the HL2 so the HL2 can operate with or without a PA/filter companion card. A PA/filter companion card may also connect to a SIL connector right at the edge of the HL2 if the RF connectors P9, P11 and P12 are not included.
4. The grounds on these connectors can be used to support and build a custom shield  of copper clad PCB and copper braid/tape around the edge.
5. CN12 provides an alternate balanced output for PA/filter companion cards.
2. Tolerances, power ratings, exact pinouts of baluns are not on the schematic. These will be in the BOM or added later to the schematic.
3. I am evaluating alternatives to the zener diode regulator used in the v1.42 frontend in terms of area, cost, functionality, availability, etc. I understand the attraction of the zener is so that input voltages less than Vop will still pass through and power the op amp.
4. U9 is an optional TR switch. To use it, FB16, FB17, C147, C148, U9 and C144 must be stuffed. To not use it, the previous components are left off and C145 and C146 are stuffed. Unlike v1.42 which tied one control pin to Vcc, this schematic uses two FPGA signals for the two control pins. This is to support other reflective switches which are in the same package but only support differential control signaling. Also, I've found that leakage through the switch is sufficient for me to make TX power, SWR, and other measurements via the RX when transmitting. No tap is necessary.
5. Currently there is just a TR switch option at build time. If installed, one can not use P11 or P12 and must use P9 as the RX input will be grounded. I am debating whether to add options for more reflective switches so that selection of P9, P11 and P12 can be dynamic. I am concerned that in the worse case the RX signal must pass through 3 of these devices with all the associated added noise, distortion and power loss. I am leaning towards running enough signals for extra switches to CN15 (6 currently, may be reduced to 4), and leave the option for further signal switching to a frontend bypass board if desired. Any input?
6. P11 is optional in a standard build. If P11 is used, P9 and P12 must be SMA. Without P11, P9 and P12 can be BNC and there is room for two pl259 connectors. In fact, P11 can't be used in the standard build and is only there for use by a frontend bypass board.

I'd appreciate any feedback on this schematic. In particular, any changes to the filters or baluns that people have made and whether the final op amp is a OPA2674 or OPA2677?

73,

Steve

KF7O

[Glenn P]

Hi Steve,

I built mine per the 1.42 values given and OPA2674. My only variation is the 24R is 22R as 24R not available here, normally.

just to be pedantic, can you add the type numbers of U9 and D5 to the schematic also, as per U8.    U8 shows two sets of supplies and gnd which may confuse some to think there are two op amps?.

glenn
vk3pe

[James Ahlstrom]

Hi Steve,

I think this looks very good.  I especially like CN12 which enables connecting a subsequent balanced amp.

I would specify an OPA2677.  I see no advantage to the OPA2674, except that the pad of the OPA2677 must be soldered down, and that will require a fine tip soldering iron.  Actually, the op amp pin out is highly standard, and many op amps could be used whatever you specify, including the OPA2674.  But I would still specify only the OPA2677 to avoid confusion.

I question the need for C31 and C32, but I guess they are there because of CN4.  On your point 5, I would have no switches, and all switching would be external, but that is just me.

The zener versus a voltage regulator is a tough problem.  The supply current can be around 100 ma, so if the HL is powered from 16 volts, you can have half a watt dissipation in the regulator.  But using a zener and not getting regulation is frustrating.

Jim

N2ADR

[PA3GSB]

Hi Steve

I looked through your design... i did not follow all the discussion.... but i like the following additions:

- Alex connector; the openhpsdr design uses ALEX used for RX and TX filtering; maybe nice to put a sort of hpsdr alex connector.

- Missing th ADC78H90 ADC.... for measuring the FWD and Rev power (also part of the alex connector)... or do you want to use the adc of the max 10 for these purposes

- use of a codec?

- hermes uses a lpf to control the vco locked to 10 Mhz... a sort of loop can also be used using the adc of the max 10 to control/ lock the clock. (i saw some posts regarding freq shift due too heat)

Goodluck with you design.

73 Johan PA3GSB

[Takashi K]

Hi Steve,

For improvement of CN4 usability, how about adding 0 ohm jumper such as the attached schematic ?

if possible,..

Also for FPGA peripheral, Is it possible to add test point(pad) or connector for audio codec TLV320AIC23B ? 

73, Takashi JI1UDD

[ZL2APV]

Hi Steve,

Looking really good. A comment on the switches. I would be unlikely to feed any circuitry connected to the V2 board with a single coax etc. feed via a changeover switch. In almost every case the following circuitry would consist of an Rx chain and a Tx chain so if fed by a changeover switch and a single coax it would require another changeover switch on the following circuitry to separate the signals again. What could be useful is 2 switches on the V2 board so both the Tx and Rx signals could be fed to two input/output connectors so that different following devices can be chosen e.g. VNA or transverter. In the case of a VNA, I am not too sure of the effect of the switches here on calibration but Jim would probably know if the VNA calibration could compensate for any switch irregularities.

73, Graeme ZL2APV

[Steve Haynal]

Hi Jim,

Thanks for the feedback. Regarding the OPA2674 vs OPA2677, I agree that the lower thermal resistance of the OPA2677 is attractive. When I run a 2 minute WSPR cycle at full power, the OPA2674 does feel pretty hot to the touch. The OPA2677 specs are slightly different which, although I don't anticipate any problems, does worry me a bit. Do you have any numbers when using the OPA2677? I would have more confidence in the OPA2677 if someone were to report some field measurements up to 10M. Another alternative is to use the OPA2674 in the 14 pin packages as the thermal resistance is slightly lower (100 C/W)  than the 8 pin package (125 C/W). This package is actually the least expensive option by about 15% at digikey. It isn't as common a footprint though.

Regarding C31 and C32, they were added to the V1.2 Hermes-Lite given this comment at the bottom of page 33 in the datasheet:

"The PGA input is self-biased at a 1.3 V common-mode level allowing maximum input voltage swings of ±1.5 V at RX+ and RX−. AC coupling the input signal to this stage via coupling capacitors (0.1 μF) is recommended to ensure that any external dc offset does not get amplified with high RxPGA gain settings, potentially exceeding the ADC input range."

But since there is no external dc offset in your design, they may not be necessary. They can be included on any expansion card if needed. Again, I'd appreciate some field measurement reports with these capacitors removed to gain confidence that there are no hidden problems with this change. One can replace them with shorts on their HL board to test.

I looked at alternate regulators. I didn't find anything in the switching category that I like. The most attractive alternative was a NCP1117 with jumpers to bypass as done in the Hermes. The overall cost of this is perhaps 30% less, but the area cost due to the bypass jumpers is more. I could go with the NCP1117 or the zener/transistor solution. What do others think? Another option is to have no regulation and spec the HL2 max voltage input at 12.6V... :)

Although I have my ideas regarding what you are thinking, could you please elaborate on why you made the two following design choices:

 * 10V for the OpAmp rather than 12V as in the Hermes.

 * 1:1 TX transformer, rather than something with a bit of voltage gain . For example, the Hermes uses a 1.5:1  and the datasheet uses a 1.17:1.

73,

Steve

KF7O

[Steve Haynal]

Hi Johan,

We made a decision for simplicity a long time ago to stick with only the Hermes J16-style relay interface on the Hermes-Lite and not use the Alex connector. I still like that decision.

I do not like the added cost of the ADC78H90 although others on this group do like the functionality. I eventually want to replace the ADC78H90 functionality by using the AD9866 in full duplex to make the readings. As a compromise, CN8 on the HL2 has the pins and the ADC78H90 interface is still in the firmware. A companion card can host the ADC78H90 as I believe John does on his card.

The VersaClock 5 used in the HL2 should address the heating drift issues we saw with the Si510 in HL1.22. The max10 we are using does not have the ADC (too expensive). We do have a 10 MHz reference input which can be used to sync the master clock via the VersaClock 5 or the optional microchip DAC if a VCTCXO is used.

73,

Steve

KF7O

[Steve Haynal]

Hi Takashi,

I'll see how tight the layout is regarding the CN4 usability changes.

For the audio codec, I also made a decision early on for simplicity and lower cost not to have audio in/out on the HL2. People have experimented with adding various codecs and I think the pins are there to support these experiments. Pins on CN8, CN9, CN10 and even CN15 can be repurposed for this.

73,

Steve

KF7O

[Steve Haynal]

Hi Graeme,

I like the TR switch option as I often run WSPR "bare foot." I agree that the most common configuration will be to feed later stages in the RX and TX chains separately. From my experience with pysdrvna and the two existing Hermes VNA programs, the VNA is pretty tolerant of switches/additions to the loop provided they are linear. I don't think we should be fearful of using reflective switches. There are good amateur HF radios such as the kx3 which uses scads of them. I plan to only include a build option for a TR switch on the HL2. The default build option will leave this switch out. Other switches can be on experimental expansion cards. I don't think there is edge room for more than two BNC/PL259  or three SMA connectors.

73,

Steve

KF7O

[James Ahlstrom]

Hi Steve,

On Friday, May 27, 2016 at 12:13:21 AM UTC-4, Steve Haynal wrote:

 The OPA2677 specs are slightly different which, although I don't anticipate any problems, does worry me a bit. Do you have any numbers when using the OPA2677?

Please check the board I sent you.   I though it had an OPA2677, but I could be wrong.  My board uses the OPA2677 and my tests were all done with that chip.   It works fine for me, but maybe someone else could try it.

Regarding C31 and C32, they were added to the V1.2 Hermes-Lite given this comment at the bottom of page 33 in the datasheet:

I saw that.  I think it is fine to include the capacitors as shown on your schematic.  This would be a meaningless design option.

 

I looked at alternate regulators. I didn't find anything in the switching category that I like. The most attractive alternative was a NCP1117 with jumpers to bypass as done in the Hermes.

I think the NCP1117 is best.  Somehow I missed it in my search for regulators.  The voltage drop is about 1.0 volts, almost as good as the 0.7 for the zener, and the regulator has thermal and current protection.  The 12.6 volt limit is a non-starter, as most "12 volt" amateur supplies are 13.6 volts.

 * 10V for the OpAmp rather than 12V as in the Hermes.

The AD9866 produces a precise output, and the op amp gain is set with 1% resistors.  The filter is not completely flat, but at 14.2 MHz we have 7.5 volts peak to peak at the output of each op amp.  At 7.2 MHz, the output voltage is 6.6 Vpp.  While looking at the 7.2 MHz output on a spectrum analyzer, I reduced the op amp supply voltage and saw a rapid increase in distortion at 9.6 volts.  So in general we need 9.6 - 6.6 volts = 3.0 volts headroom, or 1.5 volts at each rail.  The data sheet suggests 1.0 volts at each rail.  At 14.2 MHz we need a minimum 7.5 + 3.0 = 10.5 volt supply; or perhaps 9.5 volts for a bit more distortion.

The ideal supply is 12.0 volts, as the op amp will (I think) perform better the higher the voltage, especially if it drives a lower output resistance.  If we use the NCP1117 with its 1.0 volt drop, and we set its output voltage to 10.5 volts, we need an input supply voltage of 11.5 volts.  If someone uses a 12 volt supply that is 5% low, the supply is 11.4 volts.  With a 13.6 volt supply 5% low we could set the NCP1117 to 11.92 volts.  I didn't really choose 10 volts, and in fact the zener supplies 11.3.  That is just the label on the schematic.  The issue is how low an input supply voltage we can tolerate.  If we are guaranteed 13.6 volts minimum, we could set the regulator to 12 volts, but I think we need to allow for lower input voltages since this is an amateur project.

 

 * 1:1 TX transformer, rather than something with a bit of voltage gain . For example, the Hermes uses a 1.5:1  and the datasheet uses a 1.17:1.

I thought the bifilar winding would provide flatter frequency response, and this demands 1:1.  Experience shows that people often have problems winding transformers, and the 1:1 is simpler.   I do note that the Hermes 1.5:1 handles more power than most, so it could replace the homebrew transformer.  But it is hard to source overseas.

Jim

N2ADR

[Steve Haynal]

Hi Jim,

Yes, I do have and OPA2677 on the board you sent me. Thanks. I've tested it up to 10M and all looks good with output >= 20 dBm even with the TR switch. It still feels quite hot to the touch, but I haven't made any proper temperature measurements. With the HL2.0 footprints, I have moved the larger hole on the bottom to hand solder thermal pads to off center. The reasoning is that solder does not have as low of heat resistance as a direct or very thin soldered connecting between where the die is and the PCB pad. I plan to do the same with OPA2677 footprint and maybe that will help a bit with heat dissipation.

I will take the NCP1117 route with voltage adjustable via resistor divider. Since we will now have a regulated voltage for this amplifier section, this opens the door to experiment with some of the MMIC amplifiers that require 8 or 9 VDC. 

The BOM page for the RF frontend is more or less finished (no power regulator yet). I've attached a copy. I went by the parts you and John Williams specified. I am a bit concerned about the capacitors in the filter. There are three different manufacturers (I'd like to have one if possible) and none of them have any particular special RF attributes. The high Q/ultralow ESR/RF parts do cost a bit more and may not be worth it. Can you and others check over this BOM and let me know if you see any problems and improvements, especially with the filter capacitors. In the attached BOM, component prices are a link that should take you to the DigiKey page for that component.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

I was able to spend time this holiday weekend working on HL2.0. In particular, I finished up the analog portion BOM and refined that schematic. I added credits to that schematic to acknowledge the contributions from Jim, Claudio and Andrew. 

I also switched to a slightly different floorplan. There were some issues with my last floorplan and the banks LVDS signals were using. This new floorplan does have the ethernet on the front (my first choice and should make others happier too). The dip switch and 10MHz reference input are now on the back. This will facilitate the "long flat" configuration better.

My next steps, hopefully done in the next week or two, are to:

1. Finish the OpAmp power supply schematic and BOM
2. Create/port footprints for the new frontend
3. Finish a handful of outstanding issues in the schematic and BOM
4. Create a final FPGA pin assignment for the latest floorplan
5. Test the final FPGA pin assignment by porting the existing HL1.22 RTL to make sure it is valid and workable

After those steps are done, I need to do more detailed floorplanning with all components, and then routing.

Files on Google Drive and Github v2.0 branch contain the latest work.

73,

Steve

KF7O

[James Ahlstrom]

Hi Steve,

On Tuesday, May 31, 2016 at 1:21:04 AM UTC-4, Steve Haynal wrote:

 I have moved the larger hole on the bottom to hand solder thermal pads to off center. The reasoning is that solder does not have as low of heat resistance as a direct or very thin soldered connecting between where the die is and the PCB pad. I plan to do the same with OPA2677 footprint and maybe that will help a bit with heat dissipation.

The professionals would put small vias from the thermal pad through to the ground plane on the bottom.  The heat dissipation comes from thermal contact with whatever copper is available, mostly the bottom in a two-sided PCB.  I see that my board has thermal isolation on the bottom pad.  This is an error.  These "thermals" help with soldering the pad to the ground plane, but (of course) interfere with heat transfer.  

I will take the NCP1117 route with voltage adjustable via resistor divider. Since we will now have a regulated voltage for this amplifier section, this opens the door to experiment with some of the MMIC amplifiers that require 8 or 9 VDC. 

This is a good idea.  The OPA2677 is characterized to work at 5 volts, and will work with anything from 5 to 12 volts.  Of course, the gain must be reduced to avoid clipping.

The BOM page for the RF frontend is more or less finished (no power regulator yet). I've attached a copy. I went by the parts you and John Williams specified. I am a bit concerned about the capacitors in the filter.

I can't imagine there would be a problem with the capacitors in the filter as long as they are NP0.  But I will look at the BOM later today once I get a new schematic.

Jim

N2ADR 

[Takashi K]

Hi Steve,

How about TPS7A4901 low dropout regulator (260mV @ 100mA) ?

But a little bit expensive, USD 3 @ Digi-key.

73, Takashi JI1UDD

[James Ahlstrom]

Hi Steve,

To be complete, I should say a few works about the back termination resistors.  These are R68 and R69 on your new v2.0 schematic.  Each op amp has 7.5 Vpp at its output.  This is a total of 15 Vpp, or 5.3 Vrms.  If the output is shorted, this will appear across the two 24 ohm resistors, and dissipate 293 mW in each.  That is why higher power resistors are used.  For a 50 ohm load, the dissipation would equal the load power, or 50 mW each.

The resistors specified are 500 mW units, but they have the same size 0806 as normal 125 mW resistors.  To achieve higher power it is important to attach as much copper as possible.  My board uses a ridiculously wide trace to the transformer pad, and this pad plus the transformer itself provides a heat sink.

You could argue that special resistors are not needed here.  I would suggest good wide traces for these resistors in case someone substitutes 125 mW resistors.

Jim

N2ADR 

[James Ahlstrom]

Hi Steve,

Here are my comments on the BOM.

The row with R57, 59, 59, 62 should be R57, 58, 59, 62.  There should be a 5% tolerance on the filter inductors.  There is a note to add 120p capacitors C138 and C141 to sharpen the filter.  The filter would have to be redesigned to make it an elliptical, and I don't think 120p is correct.  C138 and C141 should be specified as zero, or "Omitted".

Resistors R68 and R69 are 5%, not 1% (special 500 mW).  Not all resistors must be 1%.  These can be 5%:  R57, 58, 59, 62, 60, 61, 63, 64.  Having said that, I stopped buying 5% resistors because 1% (in 5% values) are the same price.  But R1 should be 1%.

For T2, the Coilcraft part number is not given.  The similar MACOM part is MABAES0060.  These parts are limited to 250 mW maximum, uncomfortably close to our power.  Most Minicircuits parts are also 250 mW.  T2 lists a Minicircuits ADT1, but there are several versions.  The version we want is ADT1-6T (if it fits) as this handles 500 mW.  It costs $15.45 quantity one, but $3.45 quantity 20.  Minicircuits doesn't seem to want to sell small quantities.

I still don't think there is any need for special filter capacitors, except that they are NP0.

Jim

N2ADR

[ZL2APV]

Hi Steve,

Thanks for posting the progress info. I am probably suggesting a solution to a problem which is not there but I notice there is no inductive filtering on the input to the TLV62130 on the power circuit. In my experience a major source of noise in switchmode PSU's comes from the input power feed to the supply and is easily fixed by inserting a choke of 3 or 4 turns on some 43 material either balun core or toroid. The problem is that the choke is physically large so if there is no noise it is not desirable to fit it but if you are having problems then that is the place to look. It will be radiated noise so usually won't show until an antenna is connected.

I am just waiting for some double sided adhesive, thermal conducting silicon rubber material to arrive so I can try fixing a U of copper sheet onto the OPA2674 to see if it aids the cooling.

Glenn VK3PE and I used off the shelf 22 ohm 0805 resistors for R68 and R69 and they are running cool but likely would not be the case under adverse load. Don't use this for any design guidance and stick with what Jim suggests. This is just to let you know what we got away with.

73, Graeme ZL2APV

[Glenn P]

Maybe spread the dissipation over two x 12R in series on the PCB?   I keep a good spread of SMD res in stock like others do I guess and its annoying if one has to purchase anything 'special' if it can be avoided.  But like Graeme I noticed no issues using 0805 parts under normal conditions.

glenn
vk3pe

[Glenn P]

Hi Jim,
There is a sort of 'rule of thumb' to convert an existing filter to elliptical.  "Drop the Inductor value to 75% of the original value, then compute the parallel cap required to get the notch in the right place". Seems to work well.

glenn
vk3pe

[Steve Haynal]

Hi Jim,

There are thermal vias on v1.22. I've been including thermal vias per the datasheets for all the v2.0 footprints. The larger hole to facilitate hand soldering is something I added. With the v2.0 footprints, this hole is off to the side to improve heat transfer from the die location. This may help with the OPA2677.

73,

Steve

KF7O

[Steve Haynal]

Hi Jim,

I've corrected the typos and resistor tolerances.

The optional capacitor values of 120pF for the elliptical filter came from John's BOM. Even though this is an option, I'd like to specify good values in the BOM. Does anyone want to figure out and test the best values?

The CoilCraft numbers are under the Mouser column, once you click on the price links. I went with CoilCraft as they are available via Mouser outside of the US and CoilCraft will sell direct within the US. Although the CoilCraft TX transformer is rated at 250mW, I think they might be conservative on this number.

I updated the minicircuits alternate for the TX balun to go directly to the ADT1-1WT which is the one I had in mind. It is rated for 0.5W. It has similar footprint, insertion loss and bandwidth as the ADT1-1.5 used on the Hermes. This is a fallback option for those who don't want to wind their own, or need an automated solution, or don't want to push the power of the CoilCraft part.

FB on the capacitors. I always prefer the least expensive option that gives decent performance. You hadn't specified part numbers in your BOM for these, but John did. I wanted to make sure there were no differences such as increased filter losses due to different capacitors. I may still try to reduce this down to one manufacturer.

73,

Steve

KF7O

[Steve Haynal]

Hi Graeme,

I'll see how much space is around the TLV62130 once I get more into a detailed layout. We can always recommend a choke on the power cord near the connector if this becomes an issue. I've seen noise like you describe with inexpensive power supplies. I'm hopeful that the TLV62130 does better.

73,

Steve

KF7O

[Steve Haynal]

Hi Glen,

Would you be willing to figure out and test the best optional capacitor values to make the RX filter elliptical? Even though they are optional, I'd like to specify good values in the BOM.

73,

Steve

KF7O

[Steve Haynal]

Hi Takashi,

That is an interesting part. I was hoping it would have the same footprint as the NCP1117. If you find any parts better than the NCP1117 with comparable price, please let me know.

73,

Steve

KF7O

[Glenn P]

Happy to do that Steve,

It will depend on if i have  a suitable Inductor to use, or can make one.   May take a few days

glenn

[Glenn P]

Steve, I am no expert in filters but using Elsie and looking to increase attenuation in the 88-108Mhz FM band, the Sch would be as follows (pics)

By a happy coincidence, 75% of  330uH current L15&L16 value, is close to 240nH as used in the Tx filter.

Pictures show attenuation above the FM band is worse but as expected for this type of filter. Return loss is also reduced to around 12dB

Overlayed on the Plot is the standard response and return loss, depicted with a "1" in the traces for easy comparisons.

Others skilled in Elsie might like to do a filter also?

>>> by the way, there is no space left in this group for pictures. I got a warning from Google during upload.

glenn
vk3pe

On Friday, June 3, 2016 at 3:23:31 PM UTC+10, Steve Haynal wrote:

[Steve Haynal]

Hi Glenn,

Have you tested a build of this filter? With my v1.25 board, I used Elsie to create a quick filter, but users told me it didn't work well, so would like to verify with a real build.

At a first, quick glance, I thought only the capacitor values needed to be defined. But stopping to think about it, the inductor values must be different too. It is a nice coincidence that  the value is 240 nH.

Maybe Andrew, who designed the original filter, wants to chime in about what the elliptic version should look like, or even if we should support an elliptic version?

I will look into the group storage space.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

This weekend I pretty much finalized the FPGA pin assignment, and ported the existing RTL to a MAX10 using the new pin assignment to flush out any problems. I discovered a several interesting things:

• The "compact" versions of the MAX10 parts, which are the least expensive and the ones I would like to use, do not support memory initialization or dual images. This is a disappointment. I will have to update the RTL so that the FIR filter coefficient tables are now RAMs that are dynamically programmed either from the onboard flash or over the ethernet with the proper values. We will not be able to support a second recovery image as I had originally hoped.
• One pin assignment which paired an output with a clock input feeding the PLL is illegal. This is a good catch and requires a few signal swaps in the pin assignment.
• With the existing firmware, we can fit 8 slice receivers into the target FPGA. This is with the FIR ROMs already replaced with RAMs.

73,

Steve

KF7O

[Glenn P]

Not yet Steve,

I will have to rob the 240nH from the Tx filter to do it, as i have no spares.

I will do so asap. Next day or so.

glenn
vk3pe

[ZL2APV]

Hello Steve and Jim,

I would like to be able to switch between 2 antennas from Quisk using the "Ant 1" and "Ant 2" button. I am hoping that it can be configured to have an output on one of the Optional Connector for Extra I/O pins but in case this is not able to be done with the present system I am requesting an enhancement to Quisk or V2 or both if necessary. I like to be able to change between my wire antenna and beam and it is very convenient to do this from the Quisk interface.

Thanks, Graeme ZL2APV

On Tuesday, May 31, 2016 at 5:34:36 PM UTC+12, Steve Haynal wrote:

[irbsu...@yahoo.co.uk]

Hi Glenn,
Just had a look at your filter mods to increase the rejection over 88-108MHz. You could try keeping the 330nH inductors and adding a 6.8pF across the first and a 10pF across the second. This retains the S11 at about 18dB over the passband and 1.5dB loss at 30MHz with >80dB rejection over 88-108MHz at least according to the simulator! (impact of the layout not included!)
How big are the local FM signals with you, can you capture a spectrum plot?
Andrew
G4XZL

[Steve Haynal]

Hi Graeme,

I assume this is an extra RF connector on the PA/filter board, not on the Hermes-Lite main board? There is an extra signal on the same connector meant for the power/SWR ADC that can be used although the relay driver/transistor will have to be on the companion card. 

For the optional PE4259 on the main board, I think that I will use that as an optional TR switch, or and optional RX1/RX2 switch with little work. 

73,

Steve

KF7O

[Steve Haynal]

Thanks for the design Andrew!

73,

Steve

KF7O

[Glenn P]

Thanks for the info Andrew. I was working from some notes i found somewhere re 75% of L.   Obviously that seems to be  a Furphy, from your findings..
I am yet to alter and sweep the Filter. Simpler is to do your suggested mods and see how it goes.

I don't actually have an issue with FM band, but its the only strong signal band where it 'might' be useful to drop the levels. More likely, nobody has  a problem with it and altering the filter is not needed !

glenn
vk3pe

[ZL2APV]

Hi Steve,

First the PE4259 on the main board. I have come around to your way of thinking as I am sure that others will want to use the main board barefoot as a whisper station and any extra switching really belongs on the PA/Filter board. It is a simple matter to fit a PE4259 onto the PA/Filter board to split back to separate RX and TX if we want to do this. Glenn and I are going to test the operation of the PA without the pre-amplifier and I am pretty sure we will wind up with spare space on this board with it likely gone due to enough RF from the main board making it redundant.

The other issue of having switching between two aerials is from Quisk having the Ant1/Ant2 button which is used to switch a relay in the HiQSDR radio mounted on the main board and changing between 2 sma connectors on Rx only to enable the main Rx chain or switch over to a separate Rx antenna like a Mag Loop etc. In my case I don't think it would be a good idea to add this relay to the main board as I believe it belongs on the filter board so what I am looking for is the toggle of the Ant1/Ant2 switch on Quisk to send a signal which is available on a pin of the  Optional Connector for Extra I/O on the main board where it can go through the appropriate buffer to drive the switching relay/s on the filter board. They can be jumpered to either switch RX only or both RX and TX as the user desires. Maybe there is already a way to do this but I wanted to flag it in case there is not.

73, Graeme ZL2APV

[Glenn P]

Andrew, et al

V1.42 Rx filter with and with out suggested 6.8pF and 10pF added.

It would appear well worthwhile to add the extra caps. ~ 10dB better attenuation in the area of the FM band. Steeper atten curve also, as expected with this filter type. Downside, about 1dB more loss in band at 30MHz.

Not able to check Return loss at present.

glenn
vk3pe


On Thursday, June 9, 2016 at 6:30:05 AM UTC+10, irbsu...@yahoo.co.uk wrote:

[Glenn P]

ps the effects up at the higher end ('bumps') are due to some crosstalk between cables in the setup here.

[irbsu...@yahoo.co.uk]

Hi Glenn,
The mods seem to be working which is good, but the notch depths are a little disappointing. Of course it will be sensitive to the layout. When I get a chance I'll breadboard it myself and report back.
I'm wondering if there might be another coupling path masking the true depths of the notch?
If you removed say, one of the parallel resonators, I wonder what the through loss would look like then, hopefully somewhat better than 50dB?
Andrew
G4XZL

[Glenn P]

Hi Andrew,

I redid the plot this morning user much shorter coax leads to the SA. Yesterday i grabbed what was 'handy'.

Using the shorter cables gives a slightly better result. Most likely cross talk as these are only RG174 cables of Chinese heritage.
A plot with no caps is given for comparison again.

What is interesting is that 6p8 or 10pF have little effect when fitted at C141 position (input end)  There would appear to be  a PCB issue here, either board capacitance effects or blow by perhaps due to the input link fitted which is not far from the output end of the first filter section.

End result, after trying all combinations is that  the  10pF at C136, is best. ie no 6p8 used.

Will be interesting to see the breadboard results also.

glenn
vk3pe

[Glenn P]

an update:-
The marker 3 is at noise floor of the SA/TG.    I upped the level of the TG to 0dBm (was -20) and the 108MHz marker "3" falls to about -84dB. Marker 2 at 88MHz stays at same level.
Fitting 6p8 at C141 gives a similar result to the previous Picture.   ie 88 and 108MHz markers around -65dB

So conclusion with my testing at least, stays the same. Fit only the 10pF C136 cap.

glenn

[Glenn P]

Plot attached...... there is only one cap fitted (10pF C136) but you can see two notches.......strays across C141/L16 ?

[Steve Haynal]

Hi Glen and Andrew,

Thanks for the testing. I will add your findings as options to the schematic and BOM.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Unfortunately not much to report this week as most of my time was spent attending my Nephew's college graduation. I am still working on the final schematic, BOM and footprints before detailed layout and routing. I have some updates on my computer, but have not committed these to github yet.

73,

Steve

KF7O

[irbsu...@yahoo.co.uk]

Hi Glenn,
What inductors did you use?
The design was based on Coilcraft 0805CS series.
Andrew

[Glenn P]

Hi Andrew

I used the 330uH inductors supplied in the 'kit'.   I am unsure what they are except blue in colour.and 0805.

glenn

[Glenn P]

Just checked Farnell here and they do appear to be Coilcraft 0805CS series.   Very tight 2% tolerance which is unusual i thought.

glenn
vk3pe

On Wednesday, June 15, 2016 at 8:17:59 AM UTC+10, irbsu...@yahoo.co.uk wrote:

[irbsu...@yahoo.co.uk]

Hi Glenn,
I bread-boarded the filter on test board today and got much the same results as you and indeed the 6.8pF/330nH notch does not really add much, I suspect there is some coupling between the inductors going on as well as via some other path as the ultimate stopband doesn't exceed 70dB. I will continue to have a look at it as time allows and report back if I make any significant improvements. However I suspect the pcb implementation is ultimately going to set the maximum stopband and notch depth at similar levels. Even with just the 10pF the improvement over the original is worth having.
Andrew
G4XZL

[Glenn P]

Hi Andrew,
Thats good you got similar results to confirm.  The input is relatively close to the output of the first section so could be blow by there. Possibly other unwanted effects from the ground plane on other side.

But adding the 10pF is well worthwhile for sure.   Just how that impacts actual use though, I don't don't know.

glenn
vk3pe

On Thursday, June 16, 2016 at 8:14:34 AM UTC+10, irbsu...@yahoo.co.uk wrote:

Hi Glenn,

[Steve Haynal]

Hi Group,

This weekend I did a lot of soul-searching regarding version 2. First, over time and getting to know the MAX 10 FPGAs better, I have soured on the idea of using them in V2 for these reasons:

• The 10M50SCE and 10M40SCE do not share a common footprint with the less expensive 10M25SCE and 10M16SCE devices. I major goal of mine with V2 is still to have the lowest cost DDC/DUC amateur transceiver possible with decent performance. Therefore, I'd eventually want to move to the smaller devices. I do not like the $57 and $51 price tag for the two larger parts and the 10M25 part is not available and the 10M16SCE part is too small to begin with. With the Red Pitaya and now Lime SDR selling in the mid $200 range, one can convert these to a QRP rig for an additional ~$60. I want a hobbyist to be able to build the HL2.0 for around $100, and then add a 5W PA and filters for around $60, or roughly half the price of doing the same with alternatives.
• Although the single supply voltage does offer some simplification, it leads to other limitations. LVDS can not run as fast with 3.3V. There is only 1 PLL in these single supply voltage variants. More power is consumed and there is a bigger threat of running the FPGA too hot.
• Also, the internal flash is nice to save board area for us, but it imposes other limitations. For the variants I wanted to use, the FIR coefficient tables and NCO tables can not be initialized with constants at startup. Another mechanism must be added to the RTL to do this initialization. In my mind, this is pretty much a showstopper for these parts not just for us but for many others. I have asked for verification of this limitation from Altera.
• Finally, the last straw for me was availability. I can't even buy the 10M50SCE or 10M40SCE part in the 144-EQFP package anywhere. Go to www.octopart.com and enter those part numbers. In fact, there are very few MAX 10 parts available in any size or package as can be seen if you go to the buy page on www.altera.com. Another test to see how widely used a part is, is to enter the part number on www.aliexpress.com. No one in China is selling any overstock from recent runs. 

So, if the MAX 10 is out of the picture, what should we use for V2? I evaluated the Zynq-based Snickerdoodle closely and decided that for me, this is an SDR project for another time. The Snickerdoodle is a great project and I hope the team is successful as I'd love to have something like that readily available. My concerns are as follows:

• Availability of product and dependency on a third party. I asked the team when the next batch of $55 boards would be available. They said $65 boards would be available in August. The $55 boards are held up because they can't source the required 512 MB LPDDR used on that version currently. This worries me.
• Price. Although this is the best deal on a Zynq-based board, even at $55 + $5 shipping it turns out to be significantly more than the alternative I will propose later for small batch runs.
• Connectors. I am not convinced that we can find low cost mating connectors. They do sell one style on their campaign page, but not the kind you need for the lower cost $55 board. They only work when the Snickerdoodle is populated with "connectors down" which costs an extra $10. Even at $1 a piece, 6-7 connectors can add to the price.
• Awkward mating with the HL V2. I never came up with a board combination that I liked in terms of space, boxability, etc. 
• Wifi bandwidth. The numbers they shared with me for Wifi bandwidth of the $55 unit were 52 Mbs. See this post. Although this is usable for SDR, it is on the low end, and I am not convinced the quality of service (stalls, drops) is good enough for SDR use. If people always have to add an optional hardwired gigabit port, then any savings of using a Snickerdoodle are diminished.
• Finally, the biggest reason to no pursue the Snickerdoodle for me was the additional work. I am having enough challenge just to find the time to finish a basic V2 that uses the existing firmware/software. I think I should focus on that. Still, I think the Snickerdoodle is a very interesting inexpensive option for SDR and would love to see what others can do with it.   
  

Now that the Snickerdoodle is also out of the picture, what is left? I looked at other FPGAs (Artix-7, Cyclone V) but decided to switch to the same Cyclone IV device but different packge that is used in the BeMicro SDK. Here are my reasons:

• Little risk with firmware. I know the existing firmware will work with little effort. :) There will most likely be other challenges with the design bring-up and I don't want many variables with the firmware. We know we can run 3 slice receivers, which is a nice amount for a budget radio. I think this can be improved with RTL and architecture changes I want to try after V2 is out.
• ROMs can be initialized with the Cyclone IV devices.
• Availability. The Cyclone IV parts are mature and widely used. I can buy them today at Mouser, Digi-Key and in China.
• The price is good. The EP4CE22E22C8N device sells for ~$35 in single quantities from US suppliers. See www.octopart.com. Better yet, and what finally convinced me, is they sell for $15 to $25 on the Chinese overstock market. See www.aliexpress.com and enter EP4CE22E22C8N. For any small batch runs built in China, these are the prices we'd pay. 
• This part is still in a 144-EQFP package which is hand-solderable. 
• There are less expensive footprint-compatible members with fewer FPGA resources for future ultra low cost direct Fourier conversion only radios.

The downsides to using the EP4CE22E22C8N are:

• An external serial EEPROM is required to store the FPGA firmware. This requires adding a small IC.
• Additional power supply voltages are required, 2.5V low current, 1.2V high current. This requires redesign of the current power supply.
• There are fewer (~87 versus ~99) IO pins. To expand the IO, I will probably add this IC. 
• Because of these additions, we will most likely have to go to a 10cm by 10cm board. This size pcb does not cost any more from Elecrow, but requires a new target enclosure. A great place to find enclosures in on ebay. Enter "aluminum enclosure 105mm 100mm" For example, see this. The 105mm is needed as the dimensions commonly used are external, and 105mm supports a 100mm wide board internally. We could also go to slightly smaller width, for example an enclosure with 100mm external width and internal width of 95mm.

I am also frustrated with the KSZ9031 gigabit ethernet PHY. It turns out that the magnetic jack currently specified in the BOM and schematic is incompatible with the KSZ9031. Any jack that I can find that is compatible is large, and/or requires fancy routing as pins don't align nicely, and/or is expensive. We are using a common RGMII interface, and I have decided to switch to the RTL8211CL and compatible TM211Q01FM22 jack. These parts are commonly used in budget gigabit interfaces as seen on the Pine64 and A64 OLinuXino. They can be sourced from China and Olimex, but not easily from US distributors. 

73,

Steve

KF7O

On Monday, June 13, 2016 at 9:09:51 PM UTC-7, Steve Haynal wrote:

Hi Group,

[Glenn P]

Hi Steve
thanks for the update.   I won't pretend to understand all that you wrote, but its good to see alternate thoughts and paths there. Parts supply is a big problem for low volume users especially.

Personally I don't have a problem with the case being up to the builder, instead of having to find a specified case..  While it's nice to have everything in a very small case, practicality of power supplies will dictate more, the final volume required for a project like this. And being LAN connected, it will probably be tucked away anyway.

glenn
vk3pe

[Alan Hopper]

Steve,

sounds like you have been having a frustrating time. 

 I share your view on the snickerdoodle, if it had a gigabit jack and hdmi built in or was as  established as a raspberry pi or arduino I would jump at it but as it is I don't think the gains outweigh the risks and cost.

I agree that keeping the cost down is key, if that means going to the cyclone IV then that is the way to go.  I am sure we can squeeze a couple more receivers in one way or another.

73 Alan 2E0NNB

[James Ahlstrom]

Hello Steve,

I see the problems with the MAX10.  And since the Cyclone V parts are all BGA, I think the Cyclone IV in 144-EQFP is an excellent choice.

I agree with you and Alan concerning the cost and availability of the Snickerdoodle, and the lack of an RJ-45.

I am not sure we should replace the KSZ9031.  It has proved itself in the CVA9, and I doubt the RTL8211CL-GR is a drop-in replacement.  Replacing it could result in changes to the RTL.  I don't think the magjack should be a problem.  Microchip lists the Bel Fuse 0826-1G1T-23-F as a compatible part, and the available (Digikey $6.48) 0826-1X1T-23-F has the same 12-core design.  The dates on the data sheets are 2008 for the 0826-1G1T-23-F, and 2013 for the 0826-1X1T-23-F, so I am guessing it is a newer model with different LED colors.  There are a number of other choices in 12-core magnetics on Digikey in case I have missed something.  By now, Gig Ethernet magjacks should be a standard item.

Jim

N2ADR

[Steve Haynal]

Hi Glenn,

One reason I am switching to the Cyclone IV and RTL8211 is that they are common parts in China's Silicon Delta. I hope this will make small runs assembled in China easier and less expensive.

I definitely want to include mounting holes so that HL V2 can be installed in custom cases.

73,

Steve

KF7O

[Steve Haynal]

Hi Alan,

I am feeling much less frustrated with this change to Cyclone IV. 

It will be interesting to learn more about DFC from the presentations this weekend.

73,

Steve

KF7O

[Steve Haynal]

Hi Jim,

I agree that there is risk with switching to the RTL8211CL-GR, but I think it is worth it. I expect a few changes to the RTL due to different locations/values of the internal management registers programmed via the MDIO/MDC serial interface. But I've had to change those for every version so far, DP83848 MMI on SDK, DP83848 RMII on CV with WaveShare, and KSZ9021 RGMII on CVA9. The RGMII interface is standard and will remain the same as the CVA9. This is an inexpensive commodity part and widely available in the Silicon Delta. It was used in MacBooks from the 2008-2010 era. I find lots of helpful information, including Apple schematics. You can buy it from Olimex, Aliexpress and Ebay, although I am looking more towards small inexpensive runs (50-100) built the Silicon Delta. Compatible Ethernet jacks with magnetics are also much cheaper. 

I did consider the Bel Fuse part you linked to as well as the others mentioned in the KSZ9031 datasheet. Because the KSZ9031 uses voltage-mode transmit drivers, it typically requires a jack with extra pins, and the orientation of these pins and the pins on the KSZ9031 are such that there is no straight-forward routing. You can see what has to be done by taking a close look at the routing on the CVA9. The jack I currently have speced for the KSZ9031, which has easy routing, is incompatible. The Hermes uses a compatible jack with easy routing, but it costs $13.29 on DigiKey.

My biggest risk in my mind is EMI. I'm going with an 8-core jack, but do have a 12-core backup in mind that can be tried easily. 

73,

Steve

KF7O

 

 programmed over the 

[James Ahlstrom]

Hello Steve,

I see that the RTL8211CL-GR is well worth considering.  But it runs from 1.0 volts instead of 1.2, and will require another supply.  The FPGA uses a 1.2 volt supply.  Sigh.  There always seems to be something....

Jim

N2ADR

[Steve Haynal]

Hi Jim and Group,

I am switching back to the KSZ9031RNXCC. This should please Jim. Last night I was looking at other designs that use the Cyclone IV to see how others solved various problems, and I discovered that the MyriadRF Stream project uses a KSZ9021 and the same RJ45 jack as on the CVA9 but has very clean routing to the RJ45 jack. They share their KiCAD files on github. Their routing is clean because they swap two of the differential pairs to the RJ45 jack, which I thought was illegal based on what was done on the CVA9. I went back to the KSZ9031 datasheet and learned that "Incorrect pair polarities of the differential signals are automatically corrected for all speeds." I'm not sure why the CVA9 does not use this trick to simplify routing, but now I have a straight forward way to route the KSZ9031 to a RJ45 jack on a 4 layer board. Although the expense of a KSZ9031RNXCC with compatible jack is a bit higher than a RTL8211CL+jack (around $3 more), I think it is best to stick with the proven design. I am also staying with the 8-core low profile/short RJ45 jack that is used in the CVA9 and MyriadRF Stream as it is fairly common, inexpensive ($5.73) and proven. 12-core jacks are too big.  

As I was reading the RTL8211CL layout guidelines, I was worried by the number of guidelines to reduce EMI. That made me worry people have problems meeting FCC regulations,etc., with the RTL8211CL. For the 1V supply, I was planning to use the RTL8211CL built-in switching regulator, but have no control over the switching frequency. Although it is slightly lower efficiency, I want to run all switching regulators at just above 2 MHz to prevent any birdies in amateur radio bands. In fact, I want to use a single switching device with 3 outputs so that the phase between the 3 outputs can be properly managed. A common 1.2V supply with the KS9031RN and Cyclone IV is simpler.

73,

Steve

KF7O

[Vasyl Kuzmenko]

Hi Group,
I think, we need three version of HL2.0:
1) The cheapest and the simplest.
2) middle - that you are developing
3) advanced - with more 10 slice receivers.
Every simplification and an advance is regarding digital part. Analog part should be the same, with the same quality of signal in all versions.
Many people in world does not have enough money for DUC/DDC. Also in portable operation it's not necessary to observe all frequencies. More important is energy consuming and size/weight of equipment.
I think with "middle" everything is clear. It's kind of universal device that can handle mostly all of the features and costs ~100$.
And target audience  for  "advanced" version - people that can see all frequencies at once. price > 150§. I do not understand why use set of several HL2.0, if we can just put there fancy FPGA and add +50-100$.

I think I'll be useful to join the developer team. I would like to develop the cheapest version-it's going to be like a bit advanced 1.22 version with 100mbit Ethernet.  Without SATA junction,  probably with simplified clock and etc.
I'm not really good at FPGA developing, but I can do KiCad. What is the simplest/ cuted firmware that handle all basic filtering/ethernet/menegment can be? Is it hard to simplify firmware to 16k LEs or less?


On Friday, January 29, 2016 at 7:40:04 AM UTC+1, Steve Haynal wrote:

Steve Haynal has invited you to view the following shared folder:

Hermes-Lite 2.0

Start of Hermes-Lite V2 BOM

Open

Google Drive: Have all your files within reach from any device.

[Steve Haynal]

Hi Vasyl,

I don't think there is much price squeezing that can be done. You can't fit into the 16K LEs FPGAs. The price difference between gigabit and megabit is $4-$5, but with gigabit we can eventually move some of the processing to the host pc. The ethernet mac requires 4K LEs. With approaches such as DFT or just mixing and decimation (no FIR) on the FPGA, we should be able to fit something useful in the lowest cost 6K LE FPGA, but this will require gigabit. The SATA connectors are optional. They are relatively inexpensive. I am replacing them with something else in the schematic updates I am making to switch to the Cyclone IV. You need a decent clock with low phase noise for ADC. I don't think you will beat the Versa Clock 5 solution we are targeting. You also need basic filters and external op amp for a clean signal.

73,

Steve

KF7O

[Vasyl Kuzmenko]

Hi Steave,
You are right.
Now, I would like to think about concept Raspberry PI + HL3.0 = RadioBerry )))) The idea is to offload FPGA and launch QUISK/QTRadio on RPI.
RadioBerry (https://github.com/pa3gsb/RadioBerry/) looks really interesting. The slow IO( LPF /BPF selection etc.) should be performed by Raspberry PI, and NCO + CIC + and probably FIR filters. For sure, Raspbery PI can handle 1-2Mbyte/s of samples. I mean there is no necessary to use any Ethernet.  RadioBerry can be used as server of samples to remote access, or as transceiver by itself. The C library should be written additionally for slow IO,FIR coefficients and translation samples to the ethernet(can be 127.0.0.1 for local usage) .
The choose of FPGA depends on Raspberry PI 3 GPIO + CPU performance.
Probably overall price arise ($50 RPI + FPGA + AD9866 + PCB + etc.) but it's going to be more flexible.
73,

[Sid Boyce]

Hi Vasyl,
I thought the goal here was eventually to use Gigabit Ethernet to
implement DFC.

This makes the much hyped Pi 3 a non-starter.

A better candidate all round is the ODROID-C2 - 2GHz CPU vs 1.2GHz Pi 3,
twice the memory and Gigabit Ethernet vs 100MBit of the Pi 3.

I have been running a HL 1.2 with quisk at 384K samplerate on a
ODROID-C2 with 7 inch touchscreen ever since I got the -C2 .
73 ... Sid.

On 02/07/16 07:30, Vasyl Kuzmenko wrote:
> Hi Steave,
> You are right.
> Now, I would like to think about concept Raspberry PI + HL3.0 =
> RadioBerry )))) The idea is to offload FPGA and launch QUISK/QTRadio
> on RPI.
> RadioBerry (https://github.com/pa3gsb/RadioBerry/) looks really
> interesting. The slow IO( LPF /BPF selection etc.) should be performed
> by Raspberry PI, and NCO + CIC + and probably FIR filters. For sure,
> Raspbery PI can handle 1-2Mbyte/s of samples. I mean there is no

> necessary to use any Ethernet. RadioBerry can be used as server of

> And target audience for "advanced" version - people that
> can see all frequencies at once. price > 150§. I do not

> understand why use set of several HL2.0, if we can just put
> there fancy FPGA and add +50-100$.
>
> I think I'll be useful to join the developer team. I would
> like to develop the cheapest version-it's going to be like a

> bit advanced 1.22 version with 100mbit Ethernet. Without
> SATA junction, probably with simplified clock and etc.

> I'm not really good at FPGA developing, but I can do KiCad.
> What is the simplest/ cuted firmware that handle all basic
> filtering/ethernet/menegment can be? Is it hard to simplify
> firmware to 16k LEs or less?
>
>
> On Friday, January 29, 2016 at 7:40:04 AM UTC+1, Steve Haynal
> wrote:
>

> Steve Haynal has invited you to *view* the following
> shared folder:
> Hermes-Lite 2.0
> <https://drive.google.com/folderview?id=0BykwqDPZF0aTaXU1Z2dKTUp2Wmc&usp=sharing_eid&ts=56ab0943>
> Sender's profile photoStart of Hermes-Lite V2 BOM
> Open
> <https://drive.google.com/folderview?id=0BykwqDPZF0aTaXU1Z2dKTUp2Wmc&usp=sharing_eid&ts=56ab0943>

>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> Google Drive: Have all your files within reach from any

> device. Logo for Google Drive <https://drive.google.com>
>
> --
> You received this message because you are subscribed to the Google
> Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send
> an email to hermes-lite...@googlegroups.com
> <mailto:hermes-lite...@googlegroups.com>.
> For more options, visit https://groups.google.com/d/optout.


--
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Senior Staff Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks

[Vasyl Kuzmenko]

Hi Sid!
Thank you for answer!
Probably I post in wrong place, but actually what I am talking about is a hybrid RPI/Odriod/CUBIBOARD and Hermes Lite.
Sound's 24bit samples would be delivered to ARM CPU by the SPI Bus, moreover AD9866 also has SPI bus. So basically FPGA is needed only for NCO + CIC + FIR.
It's probably (I don't know I hope you will help me to clarify that) greatly simplify FPGA firmware and all the management of AD9866/PA/LPF/BPF will be doing by C library on ARM PC using GPIO/SPI. It will accelerate developing because many people can write C code.
73.

On Saturday, July 2, 2016 at 10:08:31 AM UTC+2, Sid Boyce wrote:

Hi Vasyl,
I thought the goal here was eventually to use Gigabit Ethernet to
implement DFC.

This makes the much hyped Pi 3 a non-starter.

A better candidate all round is the ODROID-C2 - 2GHz CPU vs 1.2GHz Pi 3,
twice the memory and Gigabit Ethernet vs 100MBit of the Pi 3.

I have been running a HL 1.2 with quisk at 384K samplerate on a
ODROID-C2 with 7 inch touchscreen ever since I got the -C2 .
73 ... Sid.

[Sid Boyce]

Hi Vasyl,
Possibly, but I don't know what magic Steve weaves in the FPGA that
could be handled by C code on ARM, I only use his microcode releases for
Hermes-Lite with quisk and openHPSDRJ - both run on x86/x86_64 and ARM.

John Melton's new pihpsdr works with Hermes-Lite but currently is built
for Hermes boards, so spectrum and waterfall are OK but local audio has
not yet been implemented.

It runs on the PI2 and Pi3 using GPIO. I've tested it on ODROID-C2,
GPIO on the -C2is still to be figured out.
John's other boards are ODROID-C1+, PINE A64 and PINE A64+.

I am now working on the A64+ which has a default display of 1920x1080
which I can't find in any files, that makes the screen readable only
through a magnifier on the 7 inch HDMI screen and it fails to display on
the 1920x1080 LCD which worked with Pi1/2, ODROID-X/U3/C1/C2. The -C2
and the A64+ both use Ubuntu 16.04 LTS 64-bit but are configured
differently. The -C2 has boot.ini, the A64+ has uEnv.txt so I just need
to figure out what to edit into uEnv.txt to get 800x480.
73 ... Sid.

[Steve Haynal]

Hi Vasyl,

The audio out on the classic Hermes (Hermes-Lite has no standard local audio out) is not generated by the FPGA but by the host computer. The FPGA does the digital signal processing to convert the high speed (73.728 MHz) ADC samples down to an IQ stream of typically 48,96,192 or 384 kHz. This stream is processed by SDR software on the host computer to produce audio. The host computer's software does the demodulation (FM/SSB/CW, etc) and final filtering (2.4 kHz bandwidth, notch filters, etc.). After that, the audio is sent back to a classic Hermes over the ethernet, and a classic Hermes just has a bit of extra hardware to be a synchronized sound card. Since the audio already is at the computer, I've always considered it overly complicated to send it back to the Hermes to generate audio when I have many good commodity options for sound on the host computer. For this reason, I've left out that functionality on the Hermes-Lite and have no desire to add it back. Finally, if you want to do 100% of the SDR DSP from ADC to actual audio on the FPGA, then that requires extensive additions to the FPGA RTL.

If you look back over this list, the topic of pairing a Hermes-Lite with an inexpensive SBC comes up frequently. I think it is neat to connect a HL to an inexpensive SBC, but don't think it is a good idea to customize it for any one SBC. Ethernet is a great interface that can be used with inexpensive SBCs (we can run the interface at 100 Mb/s if needed) up to expensive computer hosts with powerful processors and GPUs. Furthermore, ethernet can work at a distance so the radio is in one room or right at the antenna but the computer I access it through is in another. If ethernet is connected to a wifi router, you can access your HL via wifi. We have people on this list who run their SDR software on cheap wifi tablets from anywhere they wish. Any other interface I have considered between HL and computer (USB, SPI, PCIe, etc.) does not allow for this separation between radio and computer. I have also priced out pairing the HL with a SBC many times to try and reduce overall expense, and given that we will need a FPGA for some processing or ADC interconnect, it always comes out less expensive to just have a slightly larger FPGA with ethernet MAC and PHY on board then to pair with any SBC. The Cyclone IV FPGAs I am now targeting range in price from $5 to $35 depending on size and quantity. Gigabit Ethernet costs $5-$10 again depending on quantity. 

I don't mean to burst your bubble, but just want to be clear that I've thought about this quite a bit and have no interest in going down the SBC path. (Integrated FPGAs with ARM CPUs like on the Zynq  or Altera SoC are a bit more tempting...) Still others have an interest in using SBCs more, and I encourage you to look at the radioberry (the creator monitors and posts to this list) as well as the pihpsdr if that is what interests you.

You mentioned you can do KiCAD. Do you have any interest in helping with the current HL 2.0 direction using KiCAD?

73,

Steve

KF7O

[Rob Frohne]

Hi Sid,

I modified John's code in pihpsdr so it works with Hermes Lite.  You can listen on your display machine's pulse audio.  I sent John a pull request, but the modification was a very small one, and I'm sure he could do it just about as fast with nothing from me.  :-)  It is here, if you want it.  I'm impressed with the wdsp solution Warren made.

73,

Rob
KL7NA

-- 
Rob Frohne, PhD, PE
Professor
EF Cross School of Engineering
Walla Walla University
100 SW 4th Street
College Place, WA 99324
(509) 527-2075

[PA3GSB]

Hi All,

A little bit outside the scope of the thread... but anyway i want to add my 2 cents...

@Sid the pihpsdr software from John also contains a local audio option (only audio out; mic channel not yet in place)

One of the configurations for the radio berry is to use the system standalone. I modified the software of John (g0orx) and added also the local audio option, a start to use the radioberry as a standalone system. See github for details.

John is also building a radioberry so he will also add his ideas to the system.

Besides the standalone version it already possible to use the radioberry with any SDR program which support the openhpsdr protocol such as powersdr.

@Vasil the radioberry uses the fpga for filtering (ddc) and sends the iq data via the SPI interface to the raspberry pi; having the IQ data gives the possibility for further processing and nice software features.. also transmitting (duc) is possible!

For more details see github.

Hope this underlines the mail of Steve and gives a little bit insight in the development around the radioberry.

73 Johan PA3GSB

[Vasyl Kuzmenko]

Hi Group,
Sorry for my horrible English, and thanks everyone for answers.
First of all HL2.0 and RadioBerry both are just amazing by itself. HL2.0 is really close to production - nobody have done anything like that. 10 Receivers channels DFT on GPU.. etc.
RadioBerry has more bugs(It is really fresh ). FPGA is too fancy for that firmware, there is no full-duplex etc. But Idea for me is really AMAZING!
Let's say  my concept will be RadioBerry2.0 or HL2.0_simple:
1) It will use cheap FPGA Cyclone IV EP4CE6E22C. Of cource we have to simplify firmware to 6000 LE's and 30 multiplier.  (Right now RadioBerry1.0 use 7400LE's and 46 multiplier). Price is only 10$!
2) FPGA is used ONLY for DSP and for transfer IQ samples to SPI bus as usual SPI slave device.
3) SPI master (SBC or FT232H on any x86 PC ) is used for receive IQ samples (I don't think that we can count on 384kHz (probably Johan knows that), but for sure 48kHz is ok) via SPI AND for setting registers on AD9866 via the SAME SPI bus.
4) Analog part the same as HL2.0 + clock part is also really good in HL2.0
Advantages:
 1) All slow management work (accept prohibitively for usual CPU/GPU  Digital Signal Processing with samplerate 73728kHz ) will be  done by program on SBC or x86. More people know C/C++ than Verilog HDL.
So any management features, like switching antenna etc, could be done by just programming GPIO  on C/C++ and additional board for that.
 2) Total "hardware" price is under 50-60$ (30$ AD9866 + FPGA 10$ +  5P49V5923 + OPA2677 + PCB + etc. ) + SBC or HOST PC.
 3) Quality of transmitting/receiving signal is going to be the same as HL2.0
 4) In a case of working in field - we can use SBC as standalone configuration.
Disadvantages:
Digital part is simple - so bandwidth SPI is smaller than Gigabit Ethernet. That's why you can't:
             1 use wide sample rate 384kHz or more.
             2 use any receivers slices. FPGA is also too simple for that.
             3 use GPU DFT. 
I'm junior developer, so I would like to hear something like - "you can't do that because FPGA has 1.2v logic and SBC usually 3.3v" (odroid has GPIO 1.8v) * , "There is no possibility to shrink DSP firmware to 30 multiplier. FIR use more than 30", "your idea is horrible , nobody needs so simple DDC/DUC" etc.

@Johan certainly RB needs some "universal" library that will bind it on Ethernet (incl. 127.0.0.1) for HiQSDR/Hermes usage by any Program as g0orx/QUISK

@Steve It would be my pleasure to participate in HL2.0 by doing some PCB development in KiCAD. Than I can do this HL2.0_simple development.

73!

[Steve Haynal]

Hi Vasyl and Group,

If you haven't already seen this, take a look at the piHPSDR presentation found at this link from the openhpsdr list. There are several cool pictures of standalone SDRs. One is by Jacinto, CU2ED, which may use a Hermes-Lite. I know he has one or two.

Regarding your FPGA questions. First, even though the core voltage for the Cyclone IV is 1.2V, you can use IO voltages of 1.2, 1.8, 2.5, 3.0 (I think), and 3.3V. The IOs are grouped into banks, and you must provide an IO bank voltage supply at the level you wish to use for that bank. With HL2, I am moving as much as I can to 2.5V logic.

Second, the number of multipliers used by the final FIR filter can be reduced for your purposes. Essentially, the final FIR filter decimates by 8 and multiplies the stream by ~968 coefficients. It uses a polyphase filter with 8 banks. So each bank applies 968/8 = 121 coefficients. With a clock rate of 73.768 MHz (HL2 will use 76.8 MHz), this means each bank can process 73.768e6/121 = ~609312 samples per second. Therefore the maximum output for a single receiver on the HL is ~600kHz. 600kHz is not nicely divisible by 48000, but 384kHz and 480kHz fit and are nicely divisible. If you don't plan to support 384kHz, one possibility is to rewrite the 8 bank polyphase filter to share the same multipliers for a pair of banks, essentially each real hardware bank does the work of 2 banks in the final filter. Since each hardware instance now has to do double the work, each hardware bank instance processes 242 coefficients. This implies a maximum supported frequency of 73.728e6/242 = ~304 kHz, which will work for streams up to 192 kHz. The benefit is that the number of multipliers required by the final FIR filter is halved.

I will keep you in mind if any KiCAD jobs come up, but sometimes it is more work to carve out a job than to just do it yourself.

Good luck with your project. You will want to incorporate ideas from Jim's v1.42 board as it is hard to get a clean TX signal from the IAMP and the TxDAC is cleaner, even according to the datasheet.

Please keep the list updated with your progress, and Johan with the RadioBerry project, as all our projects share the AD9866 but are hopefully different enough to not duplicate effort.

73,

Steve

KF7O

[Alan Hopper]

Steve, List,

I had an opportunity to see John Melton's and Kjell Karlsen's standalone radios in the flesh, they are very very neat and have killed off any remaining desire I might have had for a traditional radio.  I have stolen my son's 7" pi screen to see just how small I can pack a hermes lite in. Obviously the radioberry would be very neat here.  John mentioned his pi software will work fine with gigabit with a usb adaptor so  HL2 should be fine as long as you don't ask for too much bandwidth.

73 Alan 2E0NNB

[Rob Frohne]

Hi Steve,

Thanks for the pointer to the Freidrichshafen papers!  Does anyone have any links to the audio of the lectures?

Thanks & 73,

Rob
KL7NA

--
You received this message because you are subscribed to the Google Groups "Hermes-Lite" group.

To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.

For more options, visit https://groups.google.com/d/optout.

[Sid Boyce]

Thanks Johan,
Rob has also done the same with his audio_out branch in
https://github.com/frohro/pihpsdr

John is juggling with so many balls in the air at once - Pi2/3,
ODROID-C1+/-C2, PINE A64, PINE A64+, LimeSDR, OdessySDR, and related
software/hardware projects that he must be superhuman.

Standalone is also the goal here (SDR + SBC + touchscreen + rotary
encoders/switches) - I started with the HiQSDR, a Pi 1 model B and 7
inch touch screen as seen on my QRZ.com page, then upgraded with a Pi 2
and now an ODROID-C2.

Hermes-Lite + ODROID-C2 + 7 inch touch screen with built-in speaker, not
yet standalone but with it in mind.

Later tonight or tomorrow will test pihpsdr with Hermes-Lite on the A64+.
73 ... Sid.

> --
> You received this message because you are subscribed to the Google
> Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send
> an email to hermes-lite...@googlegroups.com

> <mailto:hermes-lite...@googlegroups.com>.

> For more options, visit https://groups.google.com/d/optout.


--

[John Williams]

I also have the Pine A64+. Please share your discovery.

To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.

[Sid Boyce]

Hi all,
I always start with installing all the pre-req packages for ghpsdr3-alex
and quisk which lessens chasing them during SDR software builds.

I also build and install codec2-dev (svn co
https://svn.code.sf.net/p/freetel/code/codec2-dev) and wdsp (git clone
https://github.com/g0orx/wdsp) from source.

Probably/definitely overkill but these packages cover just about any SDR
software builds.
sudo apt-get install libfftw3-dev libasound2-dev libportaudio2
portaudio19-dev libncurses5-dev python-wxversion libusb-dev
python2.7-dev libpulse-dev build-essential subversion git autoconf
automake libtool cmake libconfig-dev libusb-0.1-4 libevent-dev
libevent-core-2.0-5 libevent-extra-2.0-5 libevent-openssl-2.0-5
libevent-pthreads-2.0-5 libssl-dev libortp-dev libortp9
libsamplerate0-dev libsamplerate0-dev libwxgtk3.0-0v5 libwxgtk3.0-dev
python-wxgtk3.0 python-wxgtk3.0-dev python3

It's up and running but with no sound, sound card 0 (HDMI sound) doesn't
exist and card 1 (USB sound) I will have to make the default to see if I
get sound.
Just using 96K samplerate as initial test.
Perhaps later versions will allow sound card selection.
Under Menu there are many options, e.g Random, Dither, etc., etc.

My 7 inch HDMI LCD on the A64+ is configured for 1920x1080 pixels so the
print has to be viewed through a magnifier but the attached snapshot is
around 6 times the size.
I am still working to get the display to 800x480 pixels as on the 2
ODROID-C2's. PINE64 decided to obfuscate, perhaps accidentally just
where it gets 1980x1020 from and BTW on the 1920x1080 22 inch LCD I got
not display at all.
73 ... Sid.

On 03/07/16 22:53, John Williams wrote:
>
> I also have the Pine A64+. Please share your discovery.
>
>
> On Sun, Jul 3, 2016, 4:06 PM Sid Boyce <boyc...@gmail.com
> <mailto:boyc...@gmail.com>> wrote:
>
> Thanks Johan,
> Rob has also done the same with his audio_out branch in
> https://github.com/frohro/pihpsdr
>
> John is juggling with so many balls in the air at once - Pi2/3,
> ODROID-C1+/-C2, PINE A64, PINE A64+, LimeSDR, OdessySDR, and related
> software/hardware projects that he must be superhuman.
>
> Standalone is also the goal here (SDR + SBC + touchscreen + rotary

> encoders/switches)Â - I started with the HiQSDR, a Pi 1 model B and 7

> <mailto:hermes-lite%2Bunsu...@googlegroups.com>
> > <mailto:hermes-lite...@googlegroups.com
> <mailto:hermes-lite%2Bunsu...@googlegroups.com>>.

> > For more options, visit https://groups.google.com/d/optout.
>
>
> --
> Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
> Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
> Senior Staff Specialist, Cricket Coach
> Microsoft Windows Free Zone - Linux used for all Computing Tasks
>
> --
> You received this message because you are subscribed to the Google
> Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it,
> send an email to hermes-lite...@googlegroups.com

> <mailto:hermes-lite%2Bunsu...@googlegroups.com>.

[Sid Boyce]

I forgot to mention ---
A 7-port powered USB hub caused the A64+ not to power up and if it was
already up, it shut down, lights out.

Using the hub without external power worked but with just keyboard and
mouse, the mouse needed replugging after power up.

I cut the +5V red wire in the cable between the hub and the A64+ so that
no longer sends +5V to cause a problem but the wall wart allows the hub
to adequately power the keyboard, mouse and USB sound card.

The problem with the 22 inch display HDMI port not displaying the A64+,
no idea, unless it chose the moment to fail to after I powered off the
monitor and moved the cable from the ODROID-U3 to the A64+ -- it has
worked fine with many SBC's over the years and the VGA port still works
to a PC.
73 ... Sid.

>> encoders/switches)Â - I started with the HiQSDR, a Pi 1 model B