External reference / GPSDO support

Jayson Bucknell

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Jul 19, 2020, 8:27:25 PM7/19/20

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Hello all, newbie user with a question. Searching the forum and the web offers no clear answer. I'm interested in interfacing a Hermes-Lite 2 with an external GPSDO reference. I have read in https://github.com/softerhardware/Hermes-Lite2/wiki/External-Clocks that this should be possible, but I can't find much information on the clock signal other than maybe frequency. Assuming I could use a Leo Bodnar or other reference to generate a clock what would good parameters be? Has anyone else done this?

Thanks!

Jayson

AA7NM

Steve Haynal

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Jul 20, 2020, 12:57:35 AM7/20/20

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Hi Jayson,

Using an external GPSDO reference has never been done with the HL2, is different from other openhpsdr radios, but something I'm interested in. The steps required are:

** Switch the clock IC to use the external CL1 clock input

** Setup the clock multipliers and dividers to generate 76.8MHz from the external reference, or pass through the clock if it is already 76.8MHz.

Unfortunately clock control is not implemented by most software. This is a HL2-specific extension. I use and test this with some modifications I made to Quisk. I should release a small Python module that allows people to set HL2-specific extensions outside of other running software. You would then install Python and run a small program which you could then enter come commands to enable/disable various new HL2 features. This will also help with the synchronous radio stuff.

The oscillator used in the HL2 is already pretty good.

https://datasheet.octopart.com/ASTXR-12-38.400MHZ-514054-T-Abracon-datasheet-66132442.pdf

We don't hear complaints about being off frequency of drift. What are you hoping to improve with a GPSDO reference? My interest is to have radios that are separated by some distance still have synchronous coherent clocks for beamforming.

73,

Steve

kf7o

73,

Steve

kf7o

Jayson Bucknell

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Jul 20, 2020, 12:21:56 PM7/20/20

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Thanks for the reply Steve. I've done a bit of WSPR and FT8 with an amplified and filtered HackRF and a GPSDO and I've had great fun on HF. Drift seems to be almost non existent. I gather the frequency stability is pretty good on the HL But I'd put in some effort to improve it the same way if I can. It's probably fine it's just me.

It sounds like I could go for generating a clock at 76.8 MHz and it shouldn't require much configuration change on the part of the HL. The Bodnars for example output a square wave. If I understand correctly, the built in TCXO in the HL is outputting a clipped sine wave at .8 volts and the clock generator takes this and outputs possibly either a clipped sine wave or square wave programmable frequency on CL2 at somewhere between 1.8 and 3.3 volts. Any idea of a minimum/maximum safe signal level for CL1? One could measure the default output waveform on CL2 I suppose. I'm not sure about potential jitter and phase noise. I would definitely be interested in trying a command prompt tool if it makes it easier/possible to get to the settings.

Jayson

AA7NM

Steve Haynal

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Jul 21, 2020, 1:09:04 AM7/21/20

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Hi Jayson,

CL1 can be setup to accept a 3.3V LVCMOS clock. It will be interesting to compare the onboard clock with a good external reference. I will try to release a Python module soon, but I've given up making promises long ago...

73,

Steve

kf7o

Ronald Nicholson

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Jul 21, 2020, 9:07:24 AM7/21/20

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Some small stand-alone python utilities to test and configure an HL2 would be great.

Would be a great help to others who I hear have spent or are still spending significant time getting the larger chucks of HL2 software (and/or the many required dependencies) built and working properly.

73,

Ron
n6ywu

Steve Haynal

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Jul 22, 2020, 11:17:14 PM7/22/20

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Hi Ron,

I've been working on this. I think I'll try to include a Jupyter (new ipython notebook) page as well so people can just open something up in a web browser can choose to run some prespecified recipes.

https://jupyter.org/

73,

Steve

kf7o

Jayson Bucknell

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Jul 28, 2020, 3:54:41 PM7/28/20

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Thanks for the information Steve. I've got a Bodnar set up and Gateware 20200727_72p2 is loaded so I think it's ready to try when you are. No hurry!

73,

Jayson

AA7NM

Phil Erickson

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Oct 22, 2020, 8:06:01 AM10/22/20

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Hi all,

Reviving this thread a bit. Is the setup in Python complicated for this particular purpose? Perhaps some simple code example could be pasted in here for hacking? (I'm comfortable in the Quisk source code, for example.). I am sure that KF7O is super-busy so not suggesting all the work for a general setup utility, but this would be interesting for experiments. It would also help me see whether a direct 10 MHz input could be used or whether another signal would have to be synthesized first before pouring it into CL1.

The interest here would not only be stabilizing long term drift for applications like continuous measurements of beacons (think WWV), but also having a known superb phase noise on the oscillator even beyond the TCXO performance.

73

Phil W1PJE

Steve Haynal

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Oct 22, 2020, 2:30:56 PM10/22/20

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Hi Phil,

Please see the hermeslite.py library. This can be used in conjunction with any running SDR software to make clock setting changes:

https://github.com/softerhardware/Hermes-Lite2/tree/master/software/hermeslite

The Jupyter notebook and github renderer shows how to use it:

https://github.com/softerhardware/Hermes-Lite2/blob/master/software/hermeslite/hermeslite.ipynb

10MHz input can be used, but the Versa5 must then be configured to provide the AD9866 with 76.8MHz.

We use this for the HL2:

https://abracon.com/Oscillators/ASTXR-12-38.400MHz-514054-T.pdf

It has worked pretty well, with good stability. We have done some phase noise analysis. It is on the older Hermes-Lite 1 github wiki:

https://github.com/softerhardware/Hermes-Lite/wiki/Clock-Phase-Noise

Currently we double the 36.8 MHz for the HL2. The thinking was that an integer doubling would be the cleanest in terms of phase noise. The AD9866 also has a builtin PLL to double the frequency, but I felt the external Versa would be cleaner and offer more flexibility. I have a HL2 where I use the AD9866 doubling direct from the oscillator, and the RadioBerry project also uses the AD9866 doubling for RX. The AD9866 has a permanent doubling for the TX so no way to bypass that. N2ADR noticed some degradation when using the Versa as a fractional PLL. I'd like to know if some other AD9866 frequencies 61.44MHz and 73.728MHz could be generated with minimal phase noise by the Versa5. This would open up some options in the gateware.

73,

Steve

kf7o

Phil Erickson

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Oct 22, 2020, 4:01:33 PM10/22/20

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Hi Steve,

Thanks. I'll absorb. If John Miles KE5FX of TimePod fame did the testing you refer to, it doesn't get better than that. Those tests look quite comprehensive. Your design choices are solid of course for minimal extra noise. Are N2ADR's degradation notes written somewhere on this mailing list?

Relative to the original idea of driving it with 10 MHz, though, the nasty spur coming through at 10 MHz with the VersaClock 6 driven through a 10 MHz reference is sobering. Presumably that's also in the VersaClock 5? - John's measurements only go to 1 MHz so I can't tell. Perhaps you always need a higher clock frequency to avoid problems (but of course, then you're getting whatever spurs the 10 MHz driven 25 MHz reference synthesizer is providing). Unfortunately, the phase noise test setup I have access to is in use at the moment (and the maser standard reference is unwell), so I'm not capable of making these types of phase noise measurements; otherwise, I'd definitely volunteer.

73

Phil W1PJE

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Phil Erickson
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keyboa...@gmail.com

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Oct 23, 2020, 2:19:48 PM10/23/20

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Hi, All. I've had no issues using the Bodnar. Exploring the settings in hermeslite.py I've worked out I can toggle the CL1 input through the PLL instead of directly with hl.enable_cl1_pll1 () and it works as well. So the clock input can be arbitrary that way? Or did it work as it was the right frequency and I need to configure a multiplier or divider for another frequency like 10MHz?

Also looking thorough the hermeslite.py file I can see how to set CL2 output to 61.44 Mhz or 76.8MHz as there is code but does one need to add or edit code for a custom frequency? For instance I'd like to output 36.0 MHz in relatively close synchronization if possible. The clock divider settings elude me.

The Jupyter Notebook gives some examples but doesn't seem to document the full range of commands. Work in progress? Maybe I'm confused but I seem to be missing information. Thoughts?

73,

Jayson

AA7NM

Phil Erickson

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Oct 23, 2020, 2:27:07 PM10/23/20

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Hi Jayson,

Just so I understand - you were feeding precisely 38.4 MHz from the Bodnar in through CL1 (replacing the onboard TCXO oscillator) that was then multiplied up by 2 internally? I too am very interested in code on how to set the numerator and divider values on the VersaClock to get correct generation of 76.8 MHz (or 61.44 MHz as an alternative, I guess?) from a user-selected input on CL1.

73

Phil W1PJE

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keyboa...@gmail.com

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Oct 23, 2020, 2:57:58 PM10/23/20

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Hi, Phil. No. I'm feeding 76.8 MHz directly from the Bodnar to the AD9866 with the command hl.enable_cl1_direct(). The command for routing thorough the PLL before the AD9866 seems to be hl.enable_cl1_pll1 (). I can test it by unhooking input from the Bodnar and watch the reception stop. It restarts when I reconnect the cable. But again I'm feeding the PLL 76.8MHz unchanged. If there are additional parameters for setting an input or it's just locking to any available signal it can detect I don't know.

Looking through the hermeslite.py class definitions I've guessed I can revert to the onboard clock with hl.disable_cl1 ().

hl.enable_cl2_sync_76p8 () seems to set CL2 out to 76.8MHz as there's code for programming the versaclock but I've no idea how to extend that.

73,

Jayson

AA7NM

Phil Erickson

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Oct 23, 2020, 3:08:10 PM10/23/20

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Hi Jayson,

Hmm, that's interesting. The crystal onboard needs a 2X multiplier to get to 76.8 MHz if I remember correctly (in the AD9866 documentation, this sets M=1 in the "2**M CLK MULTIPLIER" block, so perhaps when you set CL1 in, it resets the multiplier to 1 (M = 0). Hopefully KF7O can weigh in.

https://www.analog.com/media/en/technical-documentation/data-sheets/AD9866.pdf

73

Phil W1PJE

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Steve Haynal

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Oct 24, 2020, 12:27:45 AM10/24/20

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Hi,

hl.enable_cl1_direct() takes the direct path through the versa5 (No PLL no FOD) as seen on page 2 of the datasheet. The AD9866 needs to be configured via SPI to turn on its multiply by 2 and is entirely independent of touching the versa5. Jayson is sending his clock directly through at 76.8MHz without any use of the PLL.

There are some more comments in the hermeslite.py about how to set multipliers and divisors. See enable_cl2_61p44 in hermeslite.py.

The Versa5 is a pretty sophisticated device and it is best to look at the device documentation. All the HL2 does is pass i2c commands to it. There are links to the datasheet and programming guide here. It is useful to use the timing commander tool to configure the device and then look at which registers are changed and to what values.

73,

Steve

kf7o

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Phil Erickson

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Oct 25, 2020, 7:53:34 AM10/25/20

to Steve Haynal, Hermes-Lite

Hi Steve,

Thanks; it was easy for me to get the VersaClock 5 mixed up with the AD9866's internal capabilities. The code cleared it up. I agree that using the simple multiply by 2 from the onboard TCXO is probably the lowest phase noise one can get, but it seems there might still be some experimentation to do to figure out how bad various other settings are (and whether some of them might still be acceptable). As you said, "I'd like to know if some other AD9866 frequencies 61.44MHz and 73.728MHz could be generated with minimal phase noise by the Versa5."

Or you could do what Jayson is doing - completely external 76.8 MHz clock - which has some attractions as you can directly measure that phase noise without having to figure out the noise coming out of the VersaClock 5, buried as it is in the signal paths of the HL2.

73

Phil W1PJE

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Steve Haynal

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Oct 26, 2020, 12:06:45 AM10/26/20

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Hi Phil,

The current 76.8MHz has two factors of 5 to decimate to typical 384kHz or lower. This makes it harder to achieve some wider bandwidths, or use halfband filters. The other frequencies such as 73.728MHz (one factor of 3) and 61.44MHz (one factor of 5) have more factors of 2. Also, the AD9866 appears to get hotter faster as you near the 80MHz specification max.

I looked for Jim's comments on the Versa5 but couldn't find them. If I recall correctly, he found divisors of the form D.0 or D.5 to be okay, but saw problems with more complex fractional divisors such as D.123. I think it is possible to achieve 73.728MHz or 61.44MHz without any fractional divisors.

73,

Steve

kf7o

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