Excessive amplitude modulation using Thetis

[Conrad PA5Y]

I am now testing my HL2 with Thetis and WSJT-X. Of course, I am using VAC.

 

VAC is Voice Meter Potato – I always use this, it is the optimal solution.

 

I am using DIGU mode.

 

I see an unacceptable amount of amplitude modulation, using the VAC with same settings I do not see this behaviour using the same version of Thetis with my ANAN-100D or ANAN-7000DLE. I have tried to reduce the sample rate, which makes no difference. When I use the Thetis tune control, I do not see AM. If I use TUNE on WSJT-X I do see amplitude modulation. This can be seen on the power meter, an external receiver, and my Spectrum analyser. Due to this AM, I periodically see unacceptable spectral spreading.

 

As usual my VAC settings are as recommended here:

https://community.apache-labs.com/viewtopic.php?f=13&t=3574

 

Do others see this behaviour?

 

73

 

Conrad PA5Y

 

 

 

 

 

[Steve Haynal]

Hi Conrad,

Sorry for the delay with your first posts. New group members must have their first post approved and sometimes I don't get around to that until the weekend.

I use digital modes and haven't noticed unacceptable amplitude modulation. The HL2 gateware is different (DSP processing) from the openhpsdr gateware and as such levels and other settings may have to be changed slightly from what you are using with your ANANs. Also, I'd try something which doesn't use VAC like SparkSDR or Quisk to eliminate that the problem may be with VAC.

Regarding your CL1 and CL2 questions, CL1 is a clock input and CL2 is a clock output. These are meant not to replace the clock with a low phase noise external clock, but to daisy chain multiple HL2s together so that they are phase coherent (diversity). The CL1 input does not go directly to the ADC/DAC but the the Versa clock generator. This low jitter PLL can introduce (or reduce in some cases) phase noise. Furthermore, the AD9866 includes another PLL used to double the frequency for the DAC. The phase noise requirements for a 12-bit ADC/DAC at a lower sampling rate of 76.8MHz are not as demanding as for a 16-bit ADC/DAC sampling at over 120MHz. The Versa phase noise was measured here:

https://github.com/softerhardware/Hermes-Lite/wiki/Clock-Phase-Noise

This used lab equipment by a time nuts guy and also an employee at IDT, the manufacturer of the Versa chip. Our main concern was that the phase noise was no worse than another clock source which we had tested in the field with the original Hermes-Lite.

Information on using CL1 and CL2 is here:

https://github.com/softerhardware/Hermes-Lite2/wiki/External-Clocks

There is support for CL1 and CL2 in the hermeslite.py interface:

https://github.com/softerhardware/Hermes-Lite2/tree/master/software/hermeslite

Differences and extensions to the original openhpsdr protocol 1 are here:

https://github.com/softerhardware/Hermes-Lite2/wiki/Protocol

The HL2 is mainly about building a decent and inexpensive QRP HF DDC/DUC SDR around the AD9866 broadband modem chip, while accepting all the limitations of the AD9866. We are approaching 2000 units sold and there are many satisfied users.

73,

Steve

kf7o

[Conrad PA5Y]

Hello Steve.

 

Firstly, thanks for taking the time to reply, my questions were asked before I had time to read everything and do some of my own experiments, so my questions were premature.

 

I get that you are a fan of the HW and of course I except some of the limitations.

 

However, this AM on TX seems to be fundamentally wrong, which may be a hardware issue. The Thetis metering easily shows the problem as does my Spectrum Analyser.  I will try some different software as you suggested, most likely I will end up using SDR Console when Simon has finished with his development. I do not believe that this AM noise would not have been commented on before if it was common.

 

My VAC setup is very well proven, perhaps it is a Thetis problem.

 

‘The phase noise requirements for a 12-bit ADC/DAC at a lower sampling rate of 76.8MHz are not as demanding as for a 16-bit ADC/DAC sampling at over 120MHz’

 

I know and I know why, it’s a regular part of my profession. I am not here to attack the project Steve, merely to understand if it is suitable for my application.

 

I bought the HL2 to use with a transverter which places some extra requirements on TX PN and composite noise due to the lower band noise on VHF bands. I also use an amplifier and local band occupancy is high, so I want to be a good neighbour. It may not be good enough for 144 and 432 but most likely will be good enough for 1296 where antennas are very narrow and band occupancy is lower. Also, a typical 1296MHz transverter LO is much worse than for 144MHz and 432MHz and may dominate the performance. Measurements will help me make an informed decision. On RX the PN does not appear to be a problem with appropriate gain settings.

 

I have seen the PN plots by KE5FX and the IDT guy, they are not particularly good. What I want to do is use CL2 so that I can measure the PN of the Versa chip with an FSUP on my own hardware to make sure that things are as expected. I now know how to do this via Thetis and will measure it in the coming week. I will also measure the TX performance on 28MHz which is important for me.

 

‘We are approaching 2000 units sold and there are many satisfied users.’

 

Let’s hope that I can be another one. I have a sneaking suspicion that I may have a hardware problem.

 

73

 

Conrad PA5Y

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[G4ZAL]

Hello Conrad,

When you say you are using Thetis, are you using the Thetis version for the HL2?

https://github.com/mi0bot/OpenHPSDR-Thetis/releases/tag/v2.9.0.8-beta6

This version is specifically tailored to the hermes-Lite 2 (as opposed to 'normal' Thetis for Anan).

Maybe it makes a difference for you.

Nigel

G4ZAL

[Conrad PA5Y]

Hello Nigel, yes that is exactly what I am using.

 

Regards

 

Conrad PA5Y

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[Conrad PA5Y]

This appears to be a Thetis/HL2 problem. I do not see the amplitude modulation when using the latest SDR Console release when using the same Voice Meter Potato input and output. However, Thetis uses ASIO drivers for VAC whereas SDRC uses WASAPI. No problem with Thetis and ANAN-100D or ANAN-7000DLE when using ASIO.

 

At least I know that there is no hardware problem.

 

I have not tried SparkSDR or QUISK yet.

 

Regards

 

Conrad PA5Y

 

 

 

["Christoph v. Wüllen"]

I guess if you go "CW" and key the HL2 via the Key/PTT jack, the output amplitude is constant?

This excludes any hardware problem.

In this case, I guess the TX audio input amplitude is what varies over time.

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