ADC Overflow revisited

[scumball contractor]

Hi Steve,

I have been doing some updates to the Open Power SDR code which allows the full LNA range to be used. I have used this functionality to create an auto attenuator which will increase the gain until the ADC starts to clip and then back it off. It will attempt to increase the gain again after 100 secs (configurable). If there is no ADC clip, it will increase the gain again after another 100 secs and so on. This allows the HL2 to track the total power available for a particular band.

This all works quite well, except for 160 and 10 meters. I suspect this is because on those two bands, the HL2 is exposed to maximum power density. What I have noticed is that I get inter-mod well before I get the ADC indication via the protocol. I believed you do some processing in the gateway which means that the ADC over load is not the direct over-load from the ADC.

I looked back at a message where the ADC overload was discussed and there was talk of a number of clips been added to the protocol but I don't see it mentioned in the description in the Wiki. Was that added or is the ADC clip bit all there is?

Cheers

Reid

Gi8TME/Mi0BOT         

[Steve Haynal]

Hi Reid,

The ADC clip return is set if the ADC reaches max level for 3 ADC clock ticks between packets sent to the PC. The ADC clock is running fast at 76.8MHz so there can be up to ~200000 clock ticks or chances to increment the clip counter to 3 between packets, depending on the number and bandwidth of receivers selected. 

How are you detecting/seeing inter-mod distortion?

If I remember correctly, Alan setup similar AGC in SparkSDR. For more resolution, he uses the bandscope data, which are real samples of the ADC, to make his AGC decisions. He is often on this group but you can be sure to find him on the SparkSDR group:

 https://groups.google.com/forum/#!forum/sparksdr

73,

Steve

kf7o

[Reid Campbell]

Hi Steve,

On 06/05/2020 06:55, Steve Haynal wrote:

Hi Reid,

The ADC clip return is set if the ADC reaches max level for 3 ADC clock ticks between packets sent to the PC. The ADC clock is running fast at 76.8MHz so there can be up to ~200000 clock ticks or chances to increment the clip counter to 3 between packets, depending on the number and bandwidth of receivers selected. 

How are you detecting/seeing inter-mod distortion?

The inter-mod can be seen on the display and heard on the audio. It will happen for a second or two then the ADC bit being set will cause the gain to be reduced. On 80 metres it works seamlessly and you never notice the gain changing. The AGC will change in response to the gain change but I now compensate that and it remains unchanged.

I think you could test for it on 160 metres or set the HPF off on 80 metres . Reduce the attenuation until the ADC clips but watch the display for inter-mod before the clipping indication. I have just done that on 80 and can see inter-mod but no "ADC1 Overload".

If I remember correctly, Alan setup similar AGC in SparkSDR. For more resolution, he uses the bandscope data, which are real samples of the ADC, to make his AGC decisions. He is often on this group but you can be sure to find him on the SparkSDR group:

 https://groups.google.com/forum/#!forum/sparksdr

At this stage my knowledge of the code only allows me to skirt around the periphery of the DSP, so I was going with the indication from the HL2. I may go there is the future but there is a lot of learning.

Cheers

Reid  
Gi8TME/Mi0BOT

73,

Steve

kf7o

On Tuesday, May 5, 2020 at 12:30:37 PM UTC-7, scumball contractor wrote:

Hi Steve,

I have been doing some updates to the Open Power SDR code which allows the full LNA range to be used. I have used this functionality to create an auto attenuator which will increase the gain until the ADC starts to clip and then back it off. It will attempt to increase the gain again after 100 secs (configurable). If there is no ADC clip, it will increase the gain again after another 100 secs and so on. This allows the HL2 to track the total power available for a particular band.

This all works quite well, except for 160 and 10 meters. I suspect this is because on those two bands, the HL2 is exposed to maximum power density. What I have noticed is that I get inter-mod well before I get the ADC indication via the protocol. I believed you do some processing in the gateway which means that the ADC over load is not the direct over-load from the ADC.

I looked back at a message where the ADC overload was discussed and there was talk of a number of clips been added to the protocol but I don't see it mentioned in the description in the Wiki. Was that added or is the ADC clip bit all there is?

Cheers

Reid

Gi8TME/Mi0BOT         

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[Alan Hopper]

Hi Reid,

It's great to have someone working on powersdr, It has been a bit restrictive in the past having to maintain compatability.

I do use a combination of the ep4 wideband packet and the overload indicator for rf agc and an adc level peak meter. The wideband packet is a very small sample so is far from perfect, better feedback from the radio is still on my wish list but in honesty I found very little difference between side by side comparisons of various agc strategies so my motivation dropped.

A long time a go I had an agc mode that kept the band noise just 10db above the calibrated radio noise where possible, this generally ran at far lower gain than the 'as much gain as possible without clipping' mode. On identical radios sharing an antenna there was not a conclusive difference in wspr spot counts over 24hrs, unfortunately I did not log the results against time and I have a slight feeling that there was a pattern that changed during the day.  Re doing this is still on my ever growing todo list right next to looking at adc linearization again :)

73 Alan M0NNB

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[Reid Campbell]

Hi Alan,

On 06/05/2020 13:44, 'Alan Hopper' via Hermes-Lite wrote:

Hi Reid,

It's great to have someone working on powersdr, It has been a bit restrictive in the past having to maintain compatability.

I'm slowly getting to grips with the code but I'm was an embedded C micro controller programmer and before that Linux embedded. More happy with the control side of things or protocols. Not into DSP. Never worked this C#/.net.

I do use a combination of the ep4 wideband packet and the overload indicator for rf agc and an adc level peak meter. The wideband packet is a very small sample so is far from perfect, better feedback from the radio is still on my wish list but in honesty I found very little difference between side by side comparisons of various agc strategies so my motivation dropped.

I like to take the simple approach, adjust the gain to fill the clock, so to speak. Let the hardware tell you to back off. I told you I wasn't into DSP. It seems to work well for most of the bands as long as the ADC tells you early enough that you are hitting the limits. I'm sure someone will point me to the errors of my way.

A long time a go I had an agc mode that kept the band noise just 10db above the calibrated radio noise where possible, this generally ran at far lower gain than the 'as much gain as possible without clipping' mode. On identical radios sharing an antenna there was not a conclusive difference in wspr spot counts over 24hrs, unfortunately I did not log the results against time and I have a slight feeling that there was a pattern that changed during the day.  Re doing this is still on my ever growing todo list right next to looking at adc linearization again :)

I have a long list as well, but it involves welders and sledge hammers. I try and work on the code while my aches and pain subside.

Cheers

Reid  
Gi8TME/Mi0BOT

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[Steve Haynal]

Hi Reid and Alan,

If you two have a simple proposal to provide more useful ADC clipping indication to software without much addition or change to the existing protocol, please let me know. I'm not sure what is most useful to software here, but am willing to make changes.

The AD9866 actually doesn't have a clip indicator, and I am faking it by detecting max values of the ADC.

73,

Steve

kf7o

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[Reid Campbell]

Hi Steve,

On 08/05/2020 05:49, Steve Haynal wrote:

Hi Reid and Alan,

If you two have a simple proposal to provide more useful ADC clipping indication to software without much addition or change to the existing protocol, please let me know. I'm not sure what is most useful to software here, but am willing to make changes.

The AD9866 actually doesn't have a clip indicator, and I am faking it by detecting max values of the ADC.

Ok, that makes a difference, I thought the cliping was coming directly from the ADC. Looking at the Verilog, you look for the max positive and negative value. Is it possible that under severe overload that the ADC doesn't sit at the max value but some how rolls overs. I know it sounds unlikely but it would explain the overload without the clip being set. Maybe you have a better understanding of what is happening.

I wonder if it would help if the top/bottom 4 values set the clip indication? I am trying to download Quartus to see if I can build a custom version of the gateway - it's half way through 5.5Gb! 

Cheers

Reid
Gi8TME/Mi0BOT

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[Alan Hopper]

Hi Reid & Steve

I spent quite a while feeding signals that overloaded the adc on purpose whilst trying to map and linearize it and I'm fairly certain that on overload it behaves as the firmware assumes and sticks at the maximum or minimum value.  I shall try and remind myself what I thought would be most useful for better overload/level indication.

73 Alan M0NNB

73,

Steve

kf7o

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[Reid Campbell]

Hi Alan,

Thanks for that, it's what you would expect. Some where in the data sheet it talked about multi stage conversions, so I thought there could be a funny under high overload conditions.

You are best placed to give an alternative or possible understanding of why the clipping is not being indicated, as you have experimented in this area.

Cheers

Reid
Gi8TME/Mi0BOT

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[Steve Haynal]

Hi Reid,

Have you excluded that the IMD during overload is not coming from the software? For example, do you see the same IMD with other software?

73,

Steve

kf7o

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[Reid Campbell]

Hi Steve,

I got Quartus downloaded yesterday, was able to build the gateway and download it using SparkSDR. Was pleasantly surprised how smoothly it all went.

I played about with the clip signal, setting the threshold at different levels. I finally seen a situation where the top/bottom 16 levels gave an acceptable clipping signal which had some inter-mod on 160 but 10 metres looked clean. The inter-mod on 160 finally cleaned up after a couple of seconds and only required one step (1dB) of gain reduction.

So, I have come to the same conclusion you have, it's the inter-mod of the LNA. It looks like LNA is slightly worse performance than the ADC, I had expected it to slightly better. I only have a sample of one to compare (until a couple of weeks, second HL2 on the way) so it might be different in other units.

So, what's the conclusion? I had thought that the clip signal was generated by the ADC but that is not the case. As it is based on the data value from the ADC, it can be derived in either the gateway or the SRD software.

The current gateway solution is at top of the shop +2047, -2048. My custom build has them set at +2040 and -2041, which allows a bit of head room to allow controlling earlier control of the LNA gain. I could do this in the Power SDR software, not requiring a gateway change.

You could get clever and adjust the clip point based on the LNA setting but that would dependent on chip processing tolerances. I think I now see the way that Alan has gone with looking at the noise performance as this will take the overall system attributes into account. I'm looking for a simpler solution with acceptable performance.

Anyone, please feel free to jump in and give us your wisdom.

Cheers

Reid
Gi8TME/Mi0BOT

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[Alan Hopper]

Hi Reid,

there is some great stuff here https://www.qsl.net/in3otd/ham_radio/Hermes-Lite/RX_meas.html In my agc I jump many of the lna values and just use the steps that look best from a noise point of view but am not sure if these are the best from an IMD perspective.

73 Alan M0NNB

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[Reid Campbell]

Hi Alan,

On 10/05/2020 13:43, 'Alan Hopper' via Hermes-Lite wrote:

Hi Reid,

there is some great stuff here https://www.qsl.net/in3otd/ham_radio/Hermes-Lite/RX_meas.html In my agc I jump many of the lna values and just use the steps that look best from a noise point of view but am not sure if these are the best from an IMD perspective.

73 Alan M0NNB

Thanks for the link, some good stuff in there, I think I'll need more time to get through it all. My interest in doing an Auto Att was laziness, ever time I changed band I had to readjust the Att to get rid of the inter-mod as the band conditions had moved. I assumed it was the ADC over loading causing the issue until I wasn't seeing ADC clipping indications but still had the inter-mod.
It works for my usage model but maybe not for other operators.

I haven't had many comments on the Auto Att from the beta testers, so maybe they could chip in?

Cheers

Reid
Gi8TME/Mi0BOT 

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[Lou Scalpati]

Reid - I have not had time to install and play with the new version until last night.  I REALLY like the auto att feature.  I can skip around without fiddling...  Like I said this is a first impression since I just installed it, but thanks for that and the auto config for HL2. Thanks for digging into powersdr.  Now if someone would merge the great features that KE9NS added to the flex version.... 😎

73

Lou KI5FTY

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[Reid Campbell]

Hi Lou,

Thanks for the feedback. A friend has a Flex 3000 and made me aware of the KE9NS site, must look at it a bit closer ;-)

Cheers

Reid

[David Wilde M0WID]

Is it possible to try out your version of PowerSDR Reid? I cannot find a download anywhere.

73
Dave M0WID