An Idea for an Inexpensive Coherent DDC HF Receiver

[Steve Haynal]

Hi Group,

I've been thinking about and experimenting with an idea for a coherent DDC HF receiver under $100 for the past few months. Originally I wanted to hook several HL2s up with a coherent clock (I still may do that), but that becomes costly and complicated. I'm interested in coherent RX and TX for beamforming and wanted an inexpensive solution. The basic idea is illustrated below.

Two synchronized ADCs are on the card at the bottom right. This card is available from many sources on e-bay or aliexpress for around $30. It contains two 12-bit AD9226 ADCs with maximum sampling rate of 65 MSPS. The specs are similar to the Hermes-Lite 2.0 ADC and even slightly better in a few areas. There is no LNA in the AD9226 but there is an external AD8132. Currently, that is set for unity gain, but the gain can be set to even +20dB by changing a few resistors. At that high of a gain, there are some concerns about -3dB bandwidth (20 MHz) and noise component from the amp. So, instead of running this with single ended input as built, I plan to remove a few more resistors and configure it as a differential amp with a hand wound BN43-2402 balun converting the single ended 50Ohm to high impedance differential input to the op amp. These baluns would go where the yellow and red rectangles are. These baluns can provide some gain like a balun does on the Hermes-LIte 2.0, maybe a few dB more than the HL2. Then the amp can be configured for between +10 and +16 dB gain and hopefully provide comparable performance to the HL2. At this lower gain, we will have -3dB bandwidth larger than 30MHz, and less noise. There is no low pass antialiasing filter, so like the HL2, one option is to remove the SMA connectors and add a small board with the same antialiasing filter as the HL2 where the red rectangle and extended yellow rectangles are. Another option is just to use an inline LPF connected to the SMA connector. 

Note that it is impossible to buy 2 AD9226 and 2 AD8132 let alone the other components for less than $30 from Digi-Key or Mouser. The price would be closer to $80.

Another important component of a decent DDC SDR is a low jitter clock. As built, this card expect a clock from the FPGA, which is not a low jitter source. In the spirit of buying inexpensive boards from e-bay or aliexpress, I did consider this si5351a. But the jitter spec for that is < 70ps, better than an FPGA but still significant noise. To understand the effects of clock noise, take a look at this virtual lab and enter the ad9226 and 50ps of jitter. Then run again with 0.8 ps of jitter. The Versa Clock which we use successfully on the HL2 has a spec of 0.8 ps of jitter, which I think is acceptable for 12-bits of resolution and sampling rate of up to 65 MHz. I will do my initial testing with the Versa 5 clock evaluation board I have from designing the HL2. If the experiments are a success, I will make a small PCB for the Versa Clock IC plus oscillator (same oscillator as used on the HL2). The board will occupy the green rectangle. To keep costs down, it will be a thin 0.8 mm two layer board. I will use a VersaClock variant with 5 or more clock outputs. This is so another AD9226 card can be placed where the blue rectangle is for 4 coherent receivers. Part and PCB cost should be under $20. 

The FPGA board is from QMTECH and costs only $18. I have bought several and am impressed with the quality. It is Cyclone IV based so the initial port of HL2 RTL will be easy. It is a smaller 15K LE FPGA versus the 25K LE FPGA in the HL2, but I think I can squeeze in 4 receivers with no transmit in that space. I am not abandoning the HL2 RTL, and any work done here to squeeze in more receivers will also increase the number of receivers on the HL2. QMTECH makes several boards with the same IO connectors. There is a big brother to this board with 100K LE (4x the HL2) yet only costs $50. Note that to buy the equivalent part from Digikey would be $109. This larger capacity board also has LVDS IO with length matched routing. This is of interest to connect to some newer ADCs that use LVDS.

For connection to a host PC, I am initially using the LAN8720 board shown in the upper right corner. This costs under $2. It is only 100 Mbs, but that is enough for 4 receivers based on other work. I did look for gigabit boards but did not find an inexpensive one. One option for more bandwidth would be a $7 FT2232H board but this would require more development. It would be an opportunity to switch to soapy.

There are other options possible. Instead of 4 receivers, it is possible to put a DAC in the blue rectangle. Here is a AD9767-based board which I have already purchased. If one wants to improve the frontend performance, it is possiblel to upgrade the AD8132s to an AD8138. There are also single AD9226 boards available which can be installed in the upper left corner for 5 coherent receivers. Another possibility for the upper left corner is a GPS time module. You can also imagine small custom boards based on the AD9866 or AFE7222 or AFE7225. The VersaClock can generate quadrature clocking so you could use the two receivers to cover up to 6M. The bandwidth of the AD9226 is larger than the AD9866 so undersampling of 2M, etc., should be possible.

So far I have the ethernet working. I am about to make modifications to the AD9226 board and VersaClock generator. I also need to port and slightly tweak the HL2 receiver RTL.

I do not see this as a replacement for the HL2. Instead, I see this as a fun weekend project for homebrew DIY types. For under $100 for 2 receivers, and just over $100 for 4 receivers, you should be able to buy all the parts and put it together in a weekend with minimal surface mount soldering and rework. I do not plan to sell a kit or have any units fabricated. I may sell some PCBs in flat mailers, but it will also be inexpensive enough to order PCBs directly from China. We can organize a public shared shopping cart for the parts on DigiKey and Mouser.

The achilles heal of this project may be noise. Either from the AD8132, poor design of the PCBs or power supplies, or the AD9226. Or it may be something I don't even suspect. Experiments will show if this idea is any good. I'd appreciate any feedback or suggestions, especially ideas for the RF frontend.

73,

Steve

kf7o

[Jonas Sanamon]

Hi Steve,

Exciting ideas!  I certainly like the idea of multiple RX and TX for beam-forming. I currently have a HPSDR Atlas setup with 2 x Mercury for diversity RX but miss the possibility for TX beam-forming so I hope it will be possible to get 2 RX + 2 TX squeezed into the FPGA... Fingers crossed and I will follow this thread tightly. 

Best Regards.

Jonas - SM4VEY

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[James Ahlstrom]

Hello Steve,

I think you are right to be concerned about noise. The AD8132 has noise of 8 nV per root hertz versus the AD9866 2.4 nV at 48 dB gain. I found this reference to be useful to convert these specs to noise figure. The AD8132 has a 19 dB noise figure versus 9 dB for the AD9866. However, I measured the noise figure of the HL2 at 48 dB preamp gain to be 13.7 dB and it should be close to 9 dB. I measured this at 29 MHz and a 384 ksps rate. I am unable to account for the difference, so it would be useful if someone else could measure the noise figure. For a 30 dB preamp gain I measure an HL2 noise figure of 15.3 dB.

An ADC has a large noise figure of 30 or 40 dB, so it is useful to have gain before it. But a low noise figure is not necessary for HF due to the high antenna noise, and nowadays to our noisy RF environment. A useful exercise is to use the HL2 as a test instrument, and connect and disconnect the antenna while varying the preamp gain. At my QTH on ten meters I need 37 dB of gain so the antenna raises the noise floor by 3 dB. This doesn't include the 9 dB gain (less losses) from the transformer. But on thirty meters I only need about 6 dB. So, based on this, the input balun and 14 dB gain from the AD8132 is at least in the ball park. But since you need anti-alias filters anyway, it would be nice to squeeze in 10 dB or so of low noise gain too.

This demonstrates the huge advantage of the HL2 design which includes a low noise preamp with variable gain.

Have you thought about antennas? Maybe small loops?

Jim

N2ADR

[in3otd]

Hello Jim,
your NF measurements results are close to what I measured on my H-Lv2b3 (graph title says b2 but this was b3 actually):

the difference vs theory may come from the current noise contribution, for which I did not see a spec. in the AD9866 datasheet.
The AD8132 is a bit noisy but by putting a step-up transformer in front of it its noise figure will improve: if we go from 50 ohm to 400 ohm its NF should be around 10 dB instead of 19 dB, if I did the calculations correctly. Then of course this may impact its strong-signal handling capabilities.

73 de Claudio, DK1CG / IN3OTD

[Steve Haynal]

Hi All,

Thanks for the input. I'll go ahead with the AD8132 and try to make some measurements. If nothing else blindsides me, and the AD8132 noise is what limits performance, I will try the AD8138 or AD8139. The board uses 5V for the AD8132 so either of these devices should work. They appear to be pin and footprint compatible. Although they are relatively expensive from DigiKey or Mouser, they sell for under $2 a piece on aliexpress. Maybe they are relabeled AD8132, or maybe there is just a surplus since they have been around for ~20 years. I'll find out. :) Also the LMH6551 is another possible lower noise substitute.

For the initial configuration, I am thinking of ~499 Ohms for Rg as that is what most of the examples use. Then I'll vary Rf for gains from x3 to x10, or +9.5 to +20db. With Rg at 499 Ohms, the total differential input impedance is 1K. A 18:4 balun with center tap should bring this down to about 49.4 Ohms, and provide 13dB of gain. The Hermes-Lite Balun provides 9dB of gain. Is this asking too much from the Balun? Maybe Rg of 400 Ohms, input impedance of 800 Ohms, and a 16:4 balun with 12dB gain is better? Or should I start even lower? I'll experiment, but am happy for input.

For the antennas, I have 3 random length long wires stretched across the length of my roof. They are separated by about 6M and about 30M long. I also have a dipole in the attic. I want to use all 4 antennas. I don't want to do the rotation and addition of IQ in the gateware, but rather stream out 4 coherent IQ channels. Then in software (may hack Quisk) I will rotate complex IQ channels by some angle, multiple by some gain and add/subtract them all up. I want to create several "virtual" beam directions this way and simultaneously feed them to WSJT-X. Then I can experimentally tune the rotation and gain parameters to favor certain directions, reduce noise, etc. I'm not going for a top down mathematical approach as it would be too much for me given my random antenna setup. Instead, I am going for a bottom up empirical approach. It would also be very interesting if someone setup a regular antenna array and computed everything.

73,

Steve

kf7o

[Alan Hopper]

Hi Steve,

this is very interesting, I wonder if with 4 receivers code could put an indication of signal direction on peaks in the panascope.  I still have a orion board with twin adcs and adding support for synchronous receivers to Spark has long been on my list. Garth Swanson G3NPC recent SK was a friend and member of our local club, he was very interested in four square antennas http://www.arrl.org/files/file/QEX_Next_Issue/Sep-Oct_2013/Swanson_QEX_9_13.pdf and I always wished the orion had 4 adcs so I could emulate his work in software.  We had been working together on mapping the field of his antenna using a 3 axis field strength meter on a quadcopter but sadly did not finish it before his death.  Your proposed setup would make a very neat tuneable 3 axis field strength meter.

73 Alan M0NNB

[in3otd]

hmm, thinking a little more about it, there is something wrong with the AD9866 numbers somewhere: I think we should use the 400 ohm input impedance to calculate its NF from the voltage/current noise and this would give a much lower NF...

[arg...@mail.ru]

Hi guys! It has long been invented and works! ))) Two threads from EU1SW.
The first.
The second.

UN7RX

[Steve Haynal]

Hi UN7RX,

Thanks for the information! It is reassuring to hear that this works. It is also nice to see the Hermes-Lite RTL reused. The thread is a bit hard to follow for me. Can you provide a few more details?

** Were there any issues with noise? Were there any measurements of the noise figure, etc.?

** What was the clock source?

** Why was just a transformer and not a balun to the full differential input used at the frontend? Why 2:1?

http://www.cqham.ru/forum/attachment.php?attachmentid=290688&d=1528539208

** Was the gateware ever updated to have coherent receivers?

Just a quick look at some of the Verilog posted, the conversion to 2's complement is incorrect:

http://www.cqham.ru/forum/newreply.php?do=newreply&p=1537564

73,

Steve

kf7o

[Sergey Smolyak]

Hi, Steve,

*** AD9226 with 1:2 transformer at input have measured NF near 36 dB, that corresponds to the calculations from datasheet parameters.

*** Clocked from NV7050SA 122,88 МГц VCXO with an external divider by 2 on 74lvc74, bypassing FPGA since the first experiments showed that the FPGA outputs are very noisy for ADC clocking

*** I checked both versions, with a transformer and with fv8132. With a transformer a little less noise and intermodulation distortion.

*** Yes, some changes in the firmware were made. Now it is difficult to remember exactly what it was, it was almost 2 years ago.

*** Since we need to move from binary with a range of 0 ... 4095 to the two`s complement with a range of -2048 ... 2047 the code is correct.

73!
Serge
EU1SW

суббота, 29 июня 2019 г., 19:28:34 UTC+3 пользователь Steve Haynal написал:

[Steve Haynal]

Hi Serge,

Thanks for the response. Yes, you are correct about the two's complement conversion. I had thought the output of the ad9226 was signed magnitude, not 0 to 4095.

It looks like you are using PowerSDR? Are you able to enable "diversity" with the software and make use of two coherent receivers?

73,

Steve

kf7o

[Sergey Smolyak]

Hi!

Steve, I added code for dual ADC coherent receiver into gateware at the request of my friend Vlad, RX3QFM. I sent him a link to this thread. In his QTH noisy environment, and he was testing the PowerSDR features. I don't have a second antenna to use this feature now. But I have a plan to install a separate small “noise” antenna, maybe I will have time to do this before the end of summer. As soon as I get the results myself I will share it here. 

73!

Serge

EU1SW

воскресенье, 30 июня 2019 г., 23:13:21 UTC+3 пользователь Steve Haynal написал:

[Steve Haynal]

Hi Group,

Since I had a request for the ethernet RTL, I have started a new github repository for this project:

https://github.com/softerhardware/hazelnut

So far only the ethernet RTL is there. Inspired by Raspberry Pi, Lime SDR, Lichee Pi Zero, and Kiwi SDR, I am calling this the Hazelnut SDR. There are many commercial hazelnut orchards in the region I live.

For an ethernet connection on a FPGA, the openhpsdr RTL is a viable alternative and is pretty thrifty with resources. This particular RTL is tuned for 100 Mbs RMII. It combines the RX and TX clock domains by using the RX clock for the TX clock, which could and should probably be done to the HL2 gigabit version to save resources. Since the ethernet clock does not feed a dedicated clock pin, this version does not rely on any PLL. ICMP and DHCP are nice perks that this IP offers. One disadvantage is that this IP is not used by dozens of projects so does have some peculiarities. I've considered switching to opensource IP by Alex Forencich, https://github.com/alexforencich/verilog-ethernet, or by Enjoy-Digital, https://github.com/enjoy-digital/liteeth. 

73,

Steve

kf7o

[Esteban Benito]

Hi, is there any progress on this?  

Thanks!

73s de EA8DGL Esteban

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[Steve Haynal]

Hi Esteban,

Unfortunately no. I have all the parts ready and just need to find the time to put everything together and test.

73,

Steve

kf7o

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[Esteban Benito]

Ok, thanks :-)

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