Pure signal

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Alan Hopper

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Sep 16, 2015, 8:45:08 AM9/16/15
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Steve,
should the current full duplex firmware work with pure signal?

Does anyone know what effect pure signal has on the 2nd, 3rd,4th etc harmonics?

73
Alan M6NNB

Phil Harman

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Sep 16, 2015, 9:10:42 PM9/16/15
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If you are using receiver2.v for the off air monitor and DAC feedback then PureSignal should work with PowerSDR.
PureSignal works in the sampling bandwidth e.g. 192ksps.  It does not yet process harmonics. You could place a receiver on each of the harmonic frequencies in order to pre-process the RF signal to minimise them but this is currently WIP.

73 Phil...VK6PH 

Steve Haynal

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Sep 16, 2015, 11:55:20 PM9/16/15
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Hi Alan and Phil,

I think when I forked at ~2.5 I left out PureSignal support and haven't put it back. I'm not sure it was fully in at that point. Also, we are using the old architecture with 48 kHz bandwidth.

That is great that someone is looking at minimizing 2nd and 3rd harmonics of the TX frequency produced by the PA by sampling the harmonics and adding canceling components at the harmonic frequencies to the DA stream. We've discussed that before on this list when I did simultaneous WSPR TX on two bands. Who is working on it?

73,

Steve
KF7O

Alan Hopper

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Sep 17, 2015, 1:55:21 AM9/17/15
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Phil,
so as far as powersdr is concerned is it only the quality(flatness) of the receiver that matters, no other magic is required in the fpga?  I shall try patching receiver2.v in and see what happens.  Cancelling harmonics is something I'm very keen on, ultimately I'd like a radio with no switched tx filters that I can transmit wspr on all bands at once.  Steve has already done some of the ground work by allowing multiple transmitters in the firmware.

73 Alan M6NNB

John Laur

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Sep 17, 2015, 2:54:00 AM9/17/15
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PureSignal requires 2 RX. One must be the full rate DAC output fed
back through the receiver chain (like Steve was doing prior to full
duplex) and the other needs to be the regular receiver sampling from
the output as close to ADC full scale as ban be managed. I believe
that the PS algorithm takes care of these Rx having a time offset
automatically, but they do have to be synchronous. They are supposed
to come in on specific Rx numbers too. I think Rx5 is the DAC feedback
and Rx1 is the sampler. This may be tricky since our hardware (Except
for CVA9) cant support that many real Rx and will have to implement
dummy Rx.

To experiment with harmonic cancellation you would need to use an
extra Rx of course per harmonic.

Could be wrong about some of the specifics there -- it's entirely from memory.

73, John K5IT
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Alan Hopper

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Sep 17, 2015, 3:24:12 AM9/17/15
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John,
thanks for that, I guess it is time to get more acquainted with the powersdr source.  I'm only just starting to seriously think about this and my thoughts are rather fuzzy.  One thing that occurred to me is that the non linearity that is being measured by the current puresignal system is the same non linearity that causes the 2nd,3rd,4th etc harmonics so I not sure we need to measure it for each harmonic, can we get away with the one measure and then generate multiple tx streams.

73 Alan M6NNB

Alan Hopper

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Sep 17, 2015, 7:14:02 AM9/17/15
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Hi List,
as a first step I have got full duplex working on the cva9.  I don't pretend to understand the changes to the sdc file, I just copied what I guessed were the duplex related changes from the cv version.  Someone with better fpga skills than me had better check it, but it does seem to work.

73 
Alan M6NNB
Hermes_Lite_FD_12CVA9.zip

Steve Haynal

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Sep 17, 2015, 10:20:39 PM9/17/15
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Hi Alan,

That should do it for full duplex. Good luck!

73,

Steve
KF7O

Phil Harman

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Sep 17, 2015, 10:51:06 PM9/17/15
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Pure signal requires two receivers, one for the DAC output and the other for the RF output feedback.  The higher the sampling rate then the wider band over which you can reduce IMD. They need to be time synchronous i.e. RF, DAC, RF, DAC etc from one FIFO but not phase synchronous. You can implement PureSignal with just two receivers and that is how its done in the small FPGA that the ANAN-10E uses.

With the new protocol the Tx I&Q samples are sent at 192ksps rather than the current 48ksps.  This will improve the performance of PureSignal but it also allows us to send the envelope of the RF signal as well so we can vary the amplitude of the PA stage voltage in sympathy with the envelope and hence improve the overall PA efficiency.

You can't reduce harmonics without actually looking at the actual harmonic levels since its a close loop feedback system.  This is one area that I think DFC will assist with.  A 1kW linear with just a single VHF LPF works 'on the whiteboard'.



73 Phil...VK6PH 


Steve Haynal

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Sep 17, 2015, 11:15:30 PM9/17/15
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Hi Phil,

It was my thought that we'd have to spend a RX at each harmonic with a feedback system on the FPGA. I don't think DFC is required for this. Even with just 5 receivers as expected with the MAX10 we should be able to do quite a bit.

73,

Steve
KF7O

Steve Haynal

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Sep 17, 2015, 11:39:42 PM9/17/15
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Hi List,

Just as with pretty much all the amateur radio experimentation in SDR/DDC/DUC, research and development of these ideas has been around for a long time. You can find many articles related to linearizing a RF amplifier on scholar.google.comHere is another paper. Feedforward systems are commonly used.  

73,

Steve
KF7O

Phil Harman

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Sep 18, 2015, 1:52:16 AM9/18/15
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Hi Steve,

I did not intend to imply that DFC is required to do this, multiple receivers would produce the same effect, just that DFC may make this simpler to implement. Since this idea  has been around for so long it's interesting to speculate why it's not widely use. It's often a long journey from the whiteboard to working hardware!

73 Phil...VK6PH 

Alan Hopper

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Sep 18, 2015, 5:28:10 AM9/18/15
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Phil,
thanks for this, I modified Steve's code and I now can switch one of the receivers to return the dac output, but I have yet to convince powersdr to respond as I would expect.  For hermes with old protocol can you tell me which receiver should be used for what?  I notice the pure signal bit in the old protocol is only pulsed on for a short time when pure signal is selected in the config, what is this meant to do?
thanks again,
Alan M6NNB

Alan Hopper

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Sep 18, 2015, 12:58:04 PM9/18/15
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Phil,
sorry for the lazy questions earlier, I have looked at the powersdr source and can see that rx 4 is for the dac output and 3 for the sampled rf. I'll try and get powersdr running in the debugger this weekend which should give me some clues. I'm still intrigued what the pure signal bit does in the old protocol.
73
Alan M6NNB

John Laur

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Sep 18, 2015, 5:16:38 PM9/18/15
to Alan Hopper, Hermes-Lite
To cancel the harmonics only another Rx is necessary at the location
of each harmonic. No similar DAC feedback receiver would really be
necessary since you are trying to completely null the output. There
may end up being some kind of relationship where the two instances of
the algorithm have some interaction (ie cancelling a harmonic may
affect the IMD around the fundamental). And obviously there will be
some output power lost in the DAC when outputting multiple mixed Tx
signals.

I guess it's worth noting just to be very clear for all reading that
PureSignal is a software feature in Warrens WDSP library. The
hardware/firmware features support the algorithm only in as much as
they provide a very predictable and accurate means to measure the
distorted signal against the ideal output waveform. To implement it
you either have to 1) use WDSP or 2) write your own version of
Warren's or your own algorithm.

73, John K5IT

Phil Harman

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Sep 18, 2015, 9:32:42 PM9/18/15
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Alan,

The PureSignal bit when set connects the DAC output to a DDC input.  In which case it needs to be set whilst transmitting rather than just being pulsed.

73 Phil...VK6PH
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Alan Hopper

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Sep 19, 2015, 2:48:08 AM9/19/15
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Phil,
thanks, that is what I expected but not what powersdr 3.2.27 appears to do. With it connected to my emulator so I can see the cc data the only time the bit is set is briefly after you enable pure signal, it does not appear to be set on tx.  I just ignore it at the moment and send dac on ptt so I don't think that is causing my problem.

List,
just to be clear, all I'm trying to do at the moment is get standard pure signal working with powersdr.  I don't have any other radio that works with pure signal so one of my problems is I don't know what I should be seeing in powersdr, how quickly should it start working after clicking one of the calibrate buttons?

So far I have duplex signals being returned on the first 3 receivers and the dac op on the fourth, I can see this is correct by viewing all receivers in my software.  I wonder if the levels of the dac signal are what pure signal expects.

73 Alan M6NNB

Alan Hopper

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Sep 20, 2015, 2:43:49 AM9/20/15
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John,
yes the dac feedback should be zero for the harmonics( unless you are transmitting on multiple frequencies).   As Steve pointed out there are many approaches to this problem.  Another option might be to use the raw adc bandscope data combined with raw dac data returned not via a receiver, small chunks of this data could be used to measure the non linearity across the full badwidth of the radio.  Applying the inverse non linearity in the fpga at the output should correct all intermodulation and harmonics in one go.  This might fit neatly in a dfc solution.  I'm thinking out loud here and could be talking rubbish.

73 Alan M6NNB

Steve Haynal

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Sep 20, 2015, 11:09:48 PM9/20/15
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Hi,

I've been wondering just how dynamic an algorithm must be. It may be that all the firmware needs is a scaling coefficient and phase rotation parameters. A single RX could hop round robin through the harmonic frequencies and provide information to the host computer. The host could set these two firmware parameters. For this problem, I'm not convinced that you need a very tight loop. 

The dynamic range of the DAC also may be a problem. For the "low amplitude" segments of a SSB transmission, there may not be enough dynamic range to properly cancel the harmonics, especially when you are talking 40 to 60 dBc.

An interesting experiment would be to add a scaling coefficient and phase rotation parameters to the firmware and see how easy it would be to cancel the harmonics of a fairly steady signal like WSPR.

73,

Steve
KF7O

Alan Hopper

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Sep 21, 2015, 10:40:25 AM9/21/15
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Steve,
I like the single hopping rx idea, it could also be used to check wwv during rx.

I have had some success with pure signal. Powersdr will now correct the signal, it doesn't generally make it better but at least it is now trying.

Summary of mods
rx4 has dac output if there are enough receivers otherwise rx2 has dac output so it might work on cv or sdk if powersdr can be convinced.
rf gain control has been enabled on tx .
overload indicator enabled on tx.
the pure signal command bit is extracted but not used.

receiver output scaled X8 -  I'm sure this is not what you want but it was this that finally made pure signal attempt to work, maybe it is just the dac channel that needs scaling?

I'm using the original receiver, perhaps this is why it does not improve things or maybe it is still the levels or something silly in my beginner's verilog.


73 Alan M6NNB
puresignal.zip

Alan Hopper

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Sep 21, 2015, 4:39:37 PM9/21/15
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Pure signal is now starting to do what it should, I set the extra gain to 4x on the dac receiver and 8x on the others.  These gains could be a red herring as power sdr does not always play well with the gigabit firmware so I'm never quite sure what the invisible pure signal receivers are doing.

73 Alan M6NNB
puresignal_off.png
puresignal_on.png

Steve Haynal

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Sep 21, 2015, 11:18:16 PM9/21/15
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Hi Alan,

Nice work! I wonder if the extra gain is because of the differences in a 12-bit and 16-bit path. I calibrated the 12-bit path, but there may be some other dependency with PureSignal.

73,

Steve
KF7O

Alan Hopper

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Sep 22, 2015, 2:10:34 AM9/22/15
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Steve,
I suspect you are right that pure signal makes some assumption about signal level, I guess the best solution is to tweak powersdr rather than upset your calibrated path, I'm afraid I don't have the energy to do this at the moment, any volunteers?

This verilog development is slow work, I take my hat of to you.  If I do much more I think I'd add some debug parameters both ways to the protocol so I can tweak things without recompiling, have you any debug tips?  I don't like the way I ended up repeating the receiver code 3 times, is there a neater way?  I feel some of the ground work is now there for harmonic cancellation.

73 Alan M6NNB

John Laur

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Sep 22, 2015, 2:41:48 PM9/22/15
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The idea of using small bursts of full-rate DAC/ADC data is very
interesting. It could very well be sufficient, but at the same time
owing to how much effort was put into improving the DDC receivers to
support the current feature, it also might be that the small snippets
of data would not be sufficient to build a model to correct the most
important IMD very close to the fundamental.

Regarding the apparent levels necessary for PS to function -- some new
code was added in 3.2.27 which automatically applies adjustments to
value of the step attenuator (which in the case of Hermes-Lite does
not actually vary the value of an attenuator) in order to coax the Rx
level to be as close to ADC full scale as possible (I think it
actually aims for about -6dB of full scale) The idea is that the
corrections are better if the full dynamic range of the ADC is used.
Since the Rx preamp in the AD9866 can introduce additional IMD it
might be appropriate in "puresignal" mode to ensure that the AD9866 Rx
gain is never set above 0db. If the step-attenuator value is low
enough that preamp gain would normally be applied, it could be
substituted with a scalar multiply while the Tx is running.

The Hermes DAC is 14 bit; the feedback path in Hermes puts the full
rate DAC data back through the entire Rx chain; it may apply some
fixed gain there; I am not sure how that works or what level the
algorithm expects.

Sorry if my speculation is not that helpful. I am just trying to
recollect the information I have learned about the PS chain over time.
As far as the discussions about the algorithm itself, I think Warren
may be the only one who can talk about it to that level.

73, John K5IT

Alan Hopper

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Sep 22, 2015, 6:42:47 PM9/22/15
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John,
it was just speculation and fpga beginner's luck that got it to work, so a little more speculation can't hurt.  It would be nice to get pure signal working without messing with the calibration or powersdr.  I may well have missed something or have been fooled by other things going wrong, now I know it can work I shall try again with the standard gains just in case. The pure signal source code is not a light read and I agree Warren is probably the answer.  Getting a proper hermes Lite option in powersdr would be a good thing but I realise this is not trivial.  The preamp imd is a very good point, we should be able to measure it by changing the gain during tx.

73 Alan M6NNB

John Laur

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Sep 23, 2015, 10:04:40 AM9/23/15
to Alan Hopper, Hermes-Lite
Simplifying things, the only thing that might really need to be
tweaked either in PowerSDR or firmware is the DAC feedback level. We
already have good controls to fix up the levels coming back in over
Rx. Preventing the Rx preamp from engaging can be done later or simply
by making sure the Rf sampler feedback is sufficient enough not to
need it.

I looked at how Hermes/Angelia do it:

https://github.com/johnlaur/Angelia/blob/master/Angelia.v#L1242
temp_DACD <= {DACD, 2'b00}; // make DACD 16-bits, use high bits for DACD

So this puts the dac value into the 14 most significant bits of the 16
bit value fed to Rx4. The C equivalent would be:

temp_DACD = DACD << 2;

It is also my understanding that the preferred verilog syntax for
compiler consistency is to use bit repetition:

temp_DACD <= { DACD, { 2{1'b0} };

Since our DAC output is 12 bits you might try shifting the bits up to
the most significant positions and see if PS performs better:

DACD_16b <= { DACD_12b, { 4{1'b0} };

Putting a Hermes Lite option in powersdr is actually pretty trivial;
the real problem is the way the tests that check for these various
models are haphazard, inconsistent, and littered through the code; you
have to go and fixup every place. Most of this is doing things like
adjusting the scaling of the power meters and doing the filter
switching and the like. It's probably better to wait until the
hardware is closer to final to see how much is really needed. The
Hermes option basically opens everything up for manual control.

73, John K5IT

Alan Hopper

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Sep 23, 2015, 2:06:53 PM9/23/15
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John, list,
I've made a bit more progress, this version does not require receiver.v to be changed. I only increase the gain for the dac channel on tx and the other gains are as standard so it should work normally when not using pure signal.  Without the extra gain on the rf feedback receiver pure signal reports low feedback even when near clipping but it still works. I guess pure signal makes an assumption on the ratio of receiver output to adc output that is not true for hermes lite.

John, I put the extra gain after the receiver so as not to increase the bit depth through the receiver, I'm still using <<< as I don't think the other method will respect the sign bit at the point I'm using it.

This should work with cv or sdk if you can get powersdr to run with the  annan 10e pure signal settings.

73
Alan M6NNB
hermes_lite_core_ps.zip

John Laur

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Sep 23, 2015, 6:50:04 PM9/23/15
to Alan Hopper, Hermes-Lite
Alan,

OK,I think I understand that you are having to apply a gain on the
output of the receiver both for the DAC feedback Rx4 (what you are
calling the DAC channel) and also on Rx1 (which you are calling the RF
feedback receiver) both only during TX when the PS bit is set, right?
I would still think that shifting the DAC bits up to the highest order
before feeding the Rx4 input would at least make it more consistent
with Hermes but it's probably OK to apply gain after the Rx as well. I
really don't know if there would be any difference. The Rx input is
16bit and output is 24bit; both should be unsigned in firmware; in
PowerSDR the samples are converted almost immediately to 32bit FP.

How are you sampling the RF/feeding the Rx path in your test, and how
much power is there in your setup prior to the sampler? Regardless of
the how we end up having to make the firmware or software, it's
critical that the actual sampled signal into the Rx is as close to ADC
full scale as possible. Most of the Apache Labs radios "leak" the
signal back in through the TR relay and coupling in the filter bank;
but they also have the luxury that the "leak" is at the output of a
100W PA and so cutting it down by 10-20dB is still enough to get to
the full dynamic range of the ADC. Whatever we end up doing we
probably need to figure out a way to make PS workable in all of the
Hermes-Lite configurations: QRPp, QRP (both with internal sampler
return paths, and QRP+External PA with external sampler return path.
Applying a scaling factor to the receiver output seems like it
shouldnt be necessary if the absolute power level is correct. I wonder
what might be going on there...

Anyway, thank you for sending the test code; i will run a diff before
I continue any more rambling!

73, John K5IT

Alan Hopper

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Sep 24, 2015, 1:28:01 AM9/24/15
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John,
the last code I posted only scales the returned dac feedback rx4 and only on tx. This works but with the low feedback warning (red square). The feedback is not low as I set the rf gain to just below the the overload warning flashing, I don't think this affects operation.  I would like to be able to turn this on and off with the ps bit but powersdr does not seen to set it correctly.  

I currently have a x10 scope probe connected for feedback on an unamplified hermes lite, just what I had.

The receiver.v code has signed input and output.  As the hermes lite uses 12 bits for rx and tx it makes sense to scale after the receiver rather than increase the size of the receiver.
73 Alan M6NNB

John Laur

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Sep 24, 2015, 1:58:35 PM9/24/15
to Alan Hopper, Hermes-Lite
Alan,

See below for some helpful info from Warren on this issue including
how to access a PureSignal calibration debug menu.

Perhaps the gain being applied after Rx4 is either too much or too
little. Hopefully the diagnostic menu can characterize the problem
more precisely.

Warren also followed up to correct me - PureSignal takes the RF
sampler feedback from Rx3, not Rx1 if "Hermes" is selected as the
hardware type in PowerSDR. The receivers used by PS vary depending on
the hardware model selected; so on the Max10 for instance if 4 Rx
cannot fit we can use Rx1/2 such as in ANAN-10e.

I have not investigated how PowerSDR treats the PS bit. If it's not
doing right according to the spec, something must be fishy because it
certainly works fine with the other hardware...?

73, John K5IT


---------- Forwarded message ----------
From: Warren C. Pratt <war...@wpratt.com>
Date: Thu, Sep 24, 2015 at 11:41 AM
Subject: Re: PureSignal on the Hermes Lite
To: John Laur <john...@gmail.com>


John,

Please see comments below.

73,
Warren

On 9/24/2015 8:42 AM, John Laur wrote:
>
> Warren,
>
> Alan Hopper is trying to get PS working on the Hermes-Lite hardware.
> The discussion thread is here if you do not follow that list:
> https://groups.google.com/forum/#!topic/hermes-lite/YpNKv_TzMps

While I'm interested in the project, I have not been monitoring that
list --- too many lists and too little time, unfortunately. Please
pass along the info below.
>
>
> The primary problem is that PS indicator stays red even though Alan is
> driving the feedback signal to the analog limit of the ADC on the
> hardware. Does this indicator solely indicate a low feedback level, or
> does it actually indicate something about the relative level of the
> feedback compared to the DAC reference receiver on Rx4?

It indicates the level being returned from the receiver RELATIVE TO
the level that is expected when the ADC is at its maximum non-clipping
level. Through the down-conversion process, there is generally some
scaling that happens in the decimation process. This means that the
values returned to the software are not the same as the values coming
out of the ADC. So, to know how close we are to ADC clipping, we must
know what value is returned to software when the ADC is at its maximum
non-clipping level. There is a variable set in the software that
contains this value. Having tested various of Phil's filter designs,
I found it useful to make this value readily accessible for
experimenting. To access this value, with focus on the PureSignal
window, enter Ctrl-Alt-i . The "Calibration Information" panel will
appear in the center of the PureSignal window. "GetPk" shows you the
peak value being received back through the receiver chain for the DAC
samples ... this should be the same as the peak value that can be
delivered from the receiver returning the ADC samples. So, enter that
value in the "SetPk" area. The value you enter will not be remembered
in the database. You will see that the default "SetPk" value is now
0.4072. The "feedbk" is the precise value that is used to control the
"Feedback Level" LED. Its scale is 0 - 255.
>
>
> Since both the ADC and DAC are 12bit on this device, I suspected we
> would only need to shift the DAC output up 4 bits before feeding it
> through Rx4. Alan ended up applying this gain at the Rx4 ouputut
> instead of the input as in Hermes/Angelia/Orion. I was thinking
> perhaps the DAC reference may have too much gain on it? The normal
> (non dac feedback) Rx path should output very close to real world
> values (ie 0dBm=1mV)
>
> Would the indicator be red if there is too much phase shift between Rx1 and Rx4?

As long as Rx1 and Rx4 are identical receivers and their outputs are
synchronized, this should not be a problem. If they are different,
that's a whole 'nother can of worms.
>
>
> 73, John K5IT

Alan Hopper

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Sep 24, 2015, 4:33:11 PM9/24/15
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John, Warren,
thanks very much, using the ctrl-alt-i menu and setting the setpk to 0.12 made it all work without the extra gain, it works just the same but without the red warning. 

I then tried using the dual firs from the old protocol recevier2.v patched into Steve's receiver.v this I think gave slightly better correction but hard to tell as I am just using the fairly clean raw hermes lite.

I think I've gone as far as is useful with pure signal for the moment, it is great to see it work and good motivation for harmonic cancellation. The attached file has the extra gain removed and as far as I know should not affect anything else.  I briefly tried it on my cv and told power sdr I had an annan 10e, it refused to transmit and told me to check my antenna, maybe we need to send back dummy sensor data?

73 Alan M6NNB
hermes_lite_core_ps.zip

John Williams

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Sep 24, 2015, 5:15:00 PM9/24/15
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On the alex menu you can disable the SWR checking.
--

John Laur

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Sep 24, 2015, 6:14:40 PM9/24/15
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Alan, wonderful news! Maybe someone who has a fairly strong PA chain
can build a sampler and see how it works throught 2 amplifier stages.
This ought to yield much more satisfying performance than simply
correcting the internal non-linearity of the AD9866, but it's still
pretty impressive that even that can be improved.

Yes obviously switching to the more precise receivers for PS might be
good; but at the expense of FPGA resources -- I guess ultimately it
will come down to what will fit into the Max10 part. I think
supporting PureSignal is an extremely important feature to have in the
production unit.

If you tell PowerSDR you have ANAN-10E it expects to receive DAC
feedback on Rx2 and expects the rf sampler on Rx1. There may be also
some other incompatibilities there as well. Specifying any of the
apache labs models will expect to control each models' particular
configuration of relays on the ALEX interface. This may be part of the
reason it fails to tx.

Clearly we will need eventually to add Hermes-Lite as a special option
to PowerSDR; It should be pretty easy to do it, and I would be happy
to do it, but again I think it will be best when the hardware gets a
little more firm.

73, John K5IT

Steve Haynal

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Sep 25, 2015, 12:08:28 AM9/25/15
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HI Alan et al,

Thanks for all the work! I will take a close look at it and include it in the main repository the next time I update RTL.

73,

Steve
KF7O

Alan Hopper

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Sep 25, 2015, 3:54:12 AM9/25/15
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John,John,
thanks for that, disabling swr checking allows this to work on the cv and I guess sdk.  If the number of receivers set in the firmware is set to less than 4 it puts the dac output on rx2 to emulate an anan 10e, there maybe other issues in pretending to be a 10e but it at least means you can play with pure signal on cv/sdk.

Alan M6NNB

Steve Haynal

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Oct 11, 2015, 11:02:27 PM10/11/15
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Hi Alan,

I looked at your changes this weekend. You posted two verilog patches. Your earlier patch included changes to receiver.v to increase the gain. A later post suggests this gain is no longer needed. Is the patch to receiver.v required? This one worries me as it will effect S-meter calibration and may introduce some clipping at certain levels.  

I am also a bit concerned about not reducing the RX gain during TX if an amp is being used. I will try it with my amp and see how it works.

Thanks for the work!

73,

Steve
KF7O

Alan Hopper

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Oct 12, 2015, 1:29:39 AM10/12/15
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Steve,
The patch to receiver is not required, the debug menu in puresignal allows the gain to be set there.  You need some way to adjust the feedback level, it could be done in hardware but controlling the gain seems easiest, powersdr stores a separate gain setting for tx and I mean to add this to my software.
73 Alan M6NNB
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