This noise is jitter but the shape is not characteristic of pure phase
noise. It is however indicative of the jitter of a PLL with high loop
bandwidth and inadequate damping. I would assume in this case it is an
artifact of the DSPLL synthesizer in the Si510. If you would like to
confirm it you can inspect the clock's fundamental on your SA. I
searched around for similar plots of Si510 and I found little to
directly compare. There are some charts here
https://www.silabs.com/Support%20Documents/TechnicalDocs/How-to-Select-the-Right-PLL-based-Oscillator-for-Your-Timing-Application.pdf
that indicate its performance should normally be much better than that
as you say. It shows to be well damped and have a loop bandwidth of
300KHz. There could be a lot of things at play and we would need
additional measurements. I may borrow a SA and check things out if I
am able. I have several Hermes-Lites to compare.
73, John K5IT
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