Hermes-Lite v2.0 Design Review Help Request

[Steve Haynal]

Hello List,

Although I'm not quite at the end of my to do list, I want to put the design files out for final review. Here is how you can help:

• Review the schematic for any mistakes or questionable areas. I found one yesterday where the ground was connected to the wrong side of a capacitor. Also, most of the complex schematic symbols are being used for the first time. Check that pin outs and pin numbering are correct and that power and ground are wired.
• KiCAD does a good job at making sure that the PCB layout matches the schematic. Some footprint pin outs may be incorrect, not match the schematic pin out, or be the wrong size. There may be components that are too physically close or tall for the space available. Some ground connections may not be solid enough.

The latest schematic is attached. The latest gerber files for layout are attached. You can use gerbv to view the gerber layout files. Github, v2.0 branch, is up to date. You can check out the files with:

git clone https://github.com/softerhardware/Hermes-Lite.git

git checkout -b v2.0 origin/v2.0

The design is done with KiCAD v4.04. The design files are in Hermes-Lite/hardware/hl. Some of the schematic symbols will be missing unless you setup the libraries properly. I plan to make the libraries standalone eventually.

Here is my to do list:

1. Add connections or component near PA for thermal monitoring. This will have to be hand wired (1 or 2 wires) to the low speed ADC if used. It may be that this device is bolted directly to a TO-220.
   
2. Add narrow strip pads on sides to make electrical and thermal contact when board is slid into an enclosure. I am debating whether these pads will connect to ground on all 4 layers or just the bottom 2.
   
3. Ground pads have spoke connections for thermal relief. Some times KiCAD does not do a good job of this. Check these and add extra trace if necessary.
   
4. Finish reviewing the last 4 schematic pages for mistakes, power/ground connections, proper pinouts, and part orientation obvious from the footprint.
   
5. CL2 and Versa5 clock chip may be swapped for better return paths not crossing under AD9866 analog portion.
   
6. Create final BOM, check all complex footprints, place components on printout to verify footprints.
   
7. Tighten DRC to identify and possibly fix some problem areas.
   
8. Review datasheet layout guidelines for complex devices to make sure observed.
   
9. Consider star ground and ground return paths under AD9866.
   
10. Check I2C addressing.
    
11. Compile firmware with final pin assignment to ensure no unforeseen pin assignment problems.
    
12. Make schematic library symbols standalone, no dependencies to libraries outside of github.
    

73,

Steve

KF7O

[Alan Hopper]

Steve,

this is getting exciting, I had a quick look at the gerbers from a thermal perspective. There appear to be thermal reliefs on the ground pads for the surface mount pa option on both sides, is this intended? I guess there is an argument to keep the pa heat out of the rest of the board.  I am dubious about the small areas intended to transfer heat to the case slots from these transistors. The solder mask along the rest of the edge might prevent good contact between copper and case as it will hold the bare section away from the slot. I'm not sure if you can rely on the flatness of the slots in the case, a small error here could mean you only have a very thin line of contact.  The mask between the transistors will also prevent good contact if a bracket or spreader was bolted on. If the bracket hole was closer to the edge a simple block of metal with a hole in could be used as a spreader if a slotted case was not used.

  As I see it the major route for heat to escape from the op amp and other hot components is through the internal ground layer, it then has to pop up to the surface to be lost to the air or the case through slots or connectors, is it worth having a few more vias to the larger exposed areas of copper.  Is it worth removing the mask from the edge of the board and adding a line of vias to improve flow to the case, maybe just on the side opposite to the pa if this is a concern.

I may well be being over cautious here but being too cool is not often a problem.

I can't wait to get my hands on one, great work Steve.

73 Alan M0NNB

[Steve Haynal]

Hi Alan,

Thanks for the feedback. First, the option to mount the 2 AFT05MS003s on the main board is experimental, encouraged by Claudio's experimental observation that these transistors are not heating up too much. The fallback is to use the same small adapter boards that Claudio tested, mounted at a right angle to the main board and bolted directly to the side of the enclosure for better thermal dissipation. 

Some of the pads in the PA footprint do still have the thermal relief flag on. I do want the heat to dissipate through the entire board according to some papers I read. I do not want thermal relief here unless it is some through-hole pin that must be soldered. I will add that to my list to fix.

Once the narrow pads on the side are added, that will provide more area without solder mask for contact within the enclosure slot. I agree with you point on the internal flatness of the slot. The bracket hole can be used to press the PCB down and make better contact along the bottom of the edges. The bracket hole can not be any closer to the edge as both target enclosures has protrusions close to the edge. I will look into removing more solder mask in this area. Other options are to bolt a plate or bracket to the side of the enclosure and have the edge of that press down on the transistors. Also, short copper tape/braid may be used for heat transfer from the transistors to the side of the enclosure. The tabs on the AFT05MS003 are very small. All of this may not be enough and we will have to resort to the adapter board, but I want to give it a try. Adding the layout for the AFT05MS003 as part of the existing adapter board/TO-220 footprint did not take much additional space.

Regarding the opamp, this PCB has 4 layers instead of the 2 in Jim's design. With the thermal vias, I expect more heat to be dissipated by the inner ground planes. The opamp top layer ground pad also has more area exposed for dissipation. This added area hopefully enough to solder copper braid to for additional relief. I will look into adding more thermal vias here. The narrow pads I plan to add to the edges of the board will have solder mask removed and vias as you describe.

73,

Steve

KF7O

[Graeme Jury]

Hello Steve,

I have been working through the schematics and so far have not found anything incorrect but when I do the electrical rules check I get a number of warnings. Would you like me to try to get rid of them? It is cosmetic work but may make you feel more comfortable to not have them there.

73, Graeme zl2apv

[Graeme Jury]

Sorry, I meant to ask what is the function of the 3 resistors on sheet 1 marked PCB, CASE, PROG? Are they some kind of placeholder etc. and can I put no connects on them?

Cheers, Graeme

[Steve Haynal]

Hi Graeme,

Yes, that would be great if you can get everything in shape to run ERC. I must admit proper pin directions/types on the custom symbols for ERC has not been a high priority for me, but it is always good to have better checking. If you do get ERC going, please send me the updates or point me to your fork so that I can incorporate your improvements.

The 3 resistors on the master page are place holders for the enclosure, programmer and PCB so that they can be automatically included in the BOM via my scripts. They can and should have no connects. I will add that to my list too.

Thanks and 73,

[Phil Harman]

Hi Steve,

Layout is looking very good.  Not sure of the purpose of C10 and C11, these appear to short the external reference input to ground?  Perhaps DNI if external reference is in use.

73 Phil...VK6PH 

[Steve Haynal]

Hi Phil,

Yes, those should be DNI if the external clock reference is in use. They are there for the option to instead use the external reference pins as generic slow switch inputs. I'll update the schematic. They won't appear in the default BOM too.

Thanks and 73,

Steve

KF7O

[James Ahlstrom]

Hello Steve,

I am examining the board starting with the areas I understand the best, and have not found anything wrong yet.  I will keep looking.  I must say the board is complicated for me, and I really appreciate all the work you did to put it together.

Jim

N2ADR

[Steve Haynal]

Hi Jim and Group,

Thanks for taking a look. There is a lot going on in the PCB, but I hope it won't be considered overly complicated in the end. I suspect there will be two main build options (full with PA and instrument-only) but there are options for other experiments and configurations. I see the PCB as the hardest piece to change in the long run and want it to have some options and flexibility built in from the start.

During my reviews, I've found two additional critical bugs. One was ethernet PHY pin assignments to the FPGA that could not connect to the double data ratio IO IP used in the FPGA for the RGMII interface. This only showed up when I run a mock design through Quartus. Fortunately, there was a spare pin on the FPGA in that area and I was able to shift 10 connections to the FPGA by 1 pin to avoid this problem. The second problem was that my SOT23_3 PCB footprint had two pins swapped. This required a little rework of the board to fix.

I added mcp9700 thermal sensor footprints near the PA and was able to actually wire one up to the slow ADC so no hand wiring is necessary. 

I hope to finish the review process today.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

I ran into a major problem this evening during my review. The HL2 uses the KSZ9031RNX for the gigabit ethernet PHY. I created my footprint for this from the v2.2 datasheet. When I was mock assembling some of the larger components on a paper printout, I noticed that the thermal ground pad on the KSZ9031RNX was larger than expected and would create shorts with some vias under the IC. I discovered that the v1.0 of the datasheet had the correct larger thermal pad size. Perhaps the same part with a more recent date code has the smaller thermal pad or there is an error in the v2.2 datasheet. Either way, I have to rework that area of the layout to handle the larger thermal pad size. I now hope to submit first prototype boards for production next weekend, so there is still time for additional group review. I will post updated files with all the changes since last time soon.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Attached are the latest gerber and schematic files for further review. These files will have the date November 6 on them to distinguish from the last set.

73,

Steve

KF7O

[in3otd]

Hello Steve,
interesting; as you likely have already seen, the datasheet v2.2 in the Revision History says "Corrected  Package Information(11) and Recommended  Land Pattern  for 48-pin (7mm x 7mm)  QFN. This is a datasheet correction. There is no change to the 48-pin (7mm x 7mm) QFN package.". But it seems the device is available in two very similar packages, QFN and WQFN, which have a different center pad size.
I'm wondering if mounting a device with a small center pad on a PCB with a large pad may cause issues; the solder paste will be sized for the large pad and may be too much for the smaller size pad.

73 de Claudio, IN3OTD / DK1CG

[Steve Haynal]

Hi Claudio,

I ordered my parts from Mouser and they are definitely KSZ9031RXNCC which according to the newest datasheet is QFN with small center pad. But the pad dimension of the part matched the older datasheet. I think Mouser stock is relatively fresh. I don't now how/where/if you can find the device with the smaller pad. I think if we design for the larger pad, but create the solder paste mask for the the smaller pad, we should be okay.

73,

Steve

KF7O

[Graeme Jury]

Hi Steve,

I have hit a brick wall trying to get the schematic to have a clean ERC. The main issue is that it is not possible to internally connect 2 pins on a device so taking the simple case of a ferrite bead for example, it will be an open circuit rather than a through connection. I have looked through Kicad forums and there is a history of this problem cropping up mainly with IC's with common pins. At present the developers show no interest in fixing this although with more pressure they might as they are aware but don't see it as a priority. Other PC CAD packages do support internally connected pins on a device so there is an industry precedent for this and it is not dead in the water.

The case of the ferrite beads is the biggest occurrence as there are so many on the PSU leads. A fix is to put a PWR_FLAG on each lead but this is clumsy and fills the schematic with unnecessary symbols.

73, Graeme ZL2APV

[Steve Haynal]

Hi Graeme,

Thanks for looking into this. This is a nasty problem. There are places where I use ferrite beads to select between two IO voltages, so another potential for a short if they are internally connected. I feel pretty comfortable with the manual electrical rules checks I made.

73,

Steve

KF7O