Hermes-Lite 2.0 Updates

[Steve Haynal]

Hi Group,

To facilitate the Hermes-Lite 2.0, I've made the following online changes:

• There is now one web site with links to everything Hermes-Lite related: http://www.hermeslite.com
  This site is very simple for now but may grow in the future. 
  
• A new github repository, Hermes-Lite2, has been setup and is linked from www.hermeslite.com. All Hermes-Lite 2.x development will be here. The old repository remains for 1.x.
• There is a new Hermes-Lite 2.0beta2 Block Diagram also linked from the main site.
• There is a Hermes-Lite 2.0 Development Gallery with pictures of and comments on the new PCBs now in hand. Again, this is linked from the main site. 

Is there anyone with graphical art experience on this list? I'd love to have a logo for the Hermes-Lite. Perhaps tiny shoes with wings or something else that alludes to Hermes and Lite.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Tonight I built the 1.2V power supply as I had those parts on hand. I examined the PCBs carefully and saw that two out of five had shorts that had been fixed with small cuts on the PCB. Electrical test is included and it would seem they found a few shorts and fixed them. Claudio reported an unfixed short on one of the test PA boards. I'm not sure why that short was missed. You can see the mark from the electrical test on each of the pads. At first the power supply was producing 2.4V. The first mistake found is that the values of R14 and R15 on the schematic are swapped. R14 should be 10K, and R15 20K. After fixing that, I see a very clean 1.2V although I did not have much load.

The rest of the parts arrive this week. I plan to contact ZelPro Tuesday or Wednesday to arrange for them to do the hardest assembly work.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Here is an update on HL2beta2 prototype building progress. I completed the 1.2V, 2.5V and 3.3V power supplies and all looks good. This is enough to power everything except the RF preamp and PA. ZelPro returned with a quote, but for 6 ICs and 114 capacitors, they want $250 hand assembled or $90+$200 for reflow and a stencil. This is more than I anticipated. I've asked how much it will cost if the capacitors are left off as I am pretty comfortable and fast with those. I have started a 100% hand assembled by me unit also. This one will use parts I purchased mostly from China, the new parts will be sent to ZelPro. After great pains and a reminder that I am not very good at SMD IC assembly, I managed to solder on a FPGA from China. This was a pull so the pins were not perfectly aligned or flat and without solder. The hardest part has been device positioning and keeping it in place with all pins aligned, whether I use hot air, skillet, reflow (toaster) oven or iron. It may not work. The next step is just to get enough on the board to see if the FPGA is alive and only continue if it is. 

The end of the year is a very busy time with major work releases, school functions and family holidays.

73,

Steve

KF7O

[Steve Haynal]

ZelPro just came back with $73 for 6 ICs assembled, no capacitors. I plan to drop of the parts tomorrow.

73,

Steve

KF7O

[Sid Boyce]

Hi Steve,
That price looks reasonable to me as the most difficult parts to place
and verify are the IC's, especially the FPGA.
73 ... Sid.

> only continue if it is.Â

>
> The end of the year is a very busy time with major work releases,
> school functions and family holidays.
>
> 73,
>
> Steve
> KF7O
>
>
>

> Â

> * There is now one web site with links to everything

> Hermes-Lite related: http://www.hermeslite.com
> This site is very simple for now but may grow in the

> future.Â
> * A new github repository, Hermes-Lite2, has been setup

> and is linked from www.hermeslite.com

> <http://www.hermeslite.com>. All Hermes-Lite 2.x

> development will be here. The old repository remains
> for 1.x.

> * There is a new Hermes-Lite 2.0beta2 Block Diagram
> <https://github.com/softerhardware/Hermes-Lite2/raw/master/hardware/hl/bd.pdf>Â also

> linked from the main site.

> * There is a Hermes-Lite 2.0 Development Gallery
> <https://github.com/softerhardware/Hermes-Lite2/wiki/Development-Gallery>Â with

> pictures of and comments on the new PCBs now in hand.

> Again, this is linked from the main site.Â

>
> Is there anyone with graphical art experience on this
> list? I'd love to have a logo for the Hermes-Lite. Perhaps
> tiny shoes with wings or something else that alludes to
> Hermes and Lite.
>
> 73,
>
> Steve
> KF7O
>

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--
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Senior Staff Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks

[Steve Haynal]

Hi Group,

Here is the weekly update on my Hermes-Lite 2.0 prototype building progress. The FPGA on my handbuilt unit is alive and communicating over JTAG! This is the one with an FPGA from China that is a second-hand pull and was shipped without ESD packaging. There may still be undiscovered problems with specific IO banks or other pins. At first the nSTATUS pin never went high. This can be due to not all power supply pins connected. I borrowed a stereoscopic microscope and used an xacto knife to nudge each pin and determine if it was firmly soldered. I found ~10% of the pins were not well soldered. They were not flush with the PCB and instead were slightly raised, I suspect since this was a pulled part. After resoldering those pins, the board started to communicate over JTAG.

Today I also picked up the board from ZelPro with the 6 hardest ICs assembled. The difference between my soldering work on the handbuilt unit and their work is night and day. I will switch focus and complete the ZelPro assembled unit first. Hopefully I will be pinging the unit sometime this weekend.

[Steve Haynal]

Hi Group,

Stu and I have had an interesting private thread I wanted to share with the list. Stu added on some Hermes-Lite v2beta2 boards to another PCB order of his and has bravely decided to build one up even though there may still be some fatal flaws. Thanks Stu for taking this risk! You additional results will be helpful.

73,

Steve

KF7O

---------
Date: Thu, Dec 15, 2016 at 1:02 AM
Subject: Re: Hermes-Lite 2.0 Updates
To: Steve Haynal <st...@softerhardware.com>

Hi Steve, thanks for the info. I'll keep pushing forward with assembly.   OK to share this thread.

Stew

KF5KOG

On Dec 15, 2016 2:34 AM, "Steve Haynal" wrote:

Hi Stu,

Looks good! May I share this thread with the list? It is probably okay to assemble everything you like, but be sure to test for power supply shorts before powering it up. You could also check that the FPGA is alive. Make sure all the bypass and bulk capacitors are installed (schematic "Power" page for the FPGA) as well as R2,R3,R4,R5,R6,R7 and then see if you can detect the FPGA with Quartus and a programmer connected to CN1. 

I would leave off J22 until the clock is programmed to the proper frequency to avoid overclocking the AD9866.

The serial EERPOM for the FPGA (U1) is a wide body variant on the BOM (5.3mm) but the footprint is 3.9mm. I've ordered a couple of replacements. 

The firmware will need some changes to work with this board. One clock is now provided by the ethernet PHY. This is how it was done on the Hermes but not on the CVA9. The ethernet PHY device select address has changed. The clock will need to be programmed. This will probably be done via CN1 at first. Also the biasing levels must be set. Again, this will be a one time setting done over CN1 at first. Eventually the clock and bias will be accessible to software in the firmware.

73,

Steve

KF7O

On Wed, Dec 14, 2016 at 12:40 PM, kf5kog < wrote:

Hi Steve,

I have been working on mine too.  I ran into a problem with one of the ST1S10 regulators (1.2v)  It initially was working with resistors swapped.  As I was fiddling with the 3.3V reg to get it working the 1.2V reg stopped working.  As it turned out pin 7 apparently shorted out or nearly so at 75 ohms to ground pin 8.  Not sure what happened.  It may have been too much heat soldering bottom pad or not a good enough contact.  Replaced it today and all is good.  I've installed the difficult IC's too. Came out pretty good!

Is it OK to assemble it completely?  or is there a stage I should stop at awaiting the firmware?

I picked up some RD00HHS1 for the PA figured I'd give it a try on the HLV2.   Been doing some testing on the BX-202 1W amp with 10mw drive from Germany that uses them in a push pull configuration.  IMD results are very impressive.  I attached the article.  They are very cheap too!

73, Stew

KF5KOG

<softerh...@gmail.com>

73,

Steve

KF7O

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[Steve Haynal]

Stu's picture and paper didn't come through. They should be attached to this post.

73,

Steve

KF7O

On Thursday, December 15, 2016 at 9:21:32 AM UTC-8, Steve Haynal wrote:

Hi Group,

Stu and I have had an interesting private thread I wanted to share with the list. Stu added on some Hermes-Lite v2beta2 boards to another PCB order of his and has bravely decided to build one up even though there may still be some fatal flaws. Thanks Stu for taking this risk! You additional results will be helpful.

73,

Steve

KF7O

---------
Date: Thu, Dec 15, 2016 at 1:02 AM
Subject: Re: Hermes-Lite 2.0 Updates
To: Steve Haynal 

[Stew KF5KOG]

Hi Steve and group,

My build of the HLV2 is complete.  See attached.  I have not powered it up yet other than making sure the regulators functioned correctly in the very beginning.

The build went together fairly easy.  Most of the pads had just enough room on either side for tweezers to hold the parts.  There were a few I had to "slide" onto position.  Thanks to Steve's excellent layout!  The 0603 parts were not that difficult to place.  They do have more of a tendency to "ping" across the work bench!  Thankfully I was able to hunt the parts down or they just seemed to reappear while moving things around the bench.  I would buy a few extra passives if you decide to build.

The bottom ground pads for the IC's were easy to solder with the holes provided.  I would say out of all the difficult to solder IC's the Cyclone was the easiest once you get the placement correct.

The labeling was very good considering the limits space.  Some of the lettering was cut off on the PCB but using Kicad part finder and 3D mode worked excellent.  I can see Steve took great pains and tried to label in a logical order for the groups of passives close together.  Again, thank you Steve.

The Part numbering generally followed along the pages in the schematic so it was easy to find the parts, verify placement and check them off.  The BOM was dead on.

I decided to build the PA section according to the schematic.  I will try out the RD00HHS1 at later date.

Steve, No Hurry on the firmware. I'll be busy for the next couple of weeks.

Happy Holidays and for those that celebrate, Merry Christmas!

73, Stew

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[Stew KF5KOG]

Oh, there was one error that Steve pointed out to me.  The part for U1 in the BOM has the wider package, I managed to fit that part onto the PCB without too much trouble.  I will replace when I make another Digikey order.  Not bad considering the complexity of the project!

Stew

KF5KOG

[Steve Haynal]

Hi Stew,

Very nice looking work! I have a list of minor issues I'm keeping while building the board. I will put that on the wiki and hope you will add to it based on your experiences. T1 and T2 are not installed yet in your picture. What are you plans for those? Also, can you please post a similar photo of the bottom side?

Last night I completed the FPGA, Ethernet, Clock and AD9866 blocks for the unit I am building up. It powers up and I can see the FPGA over JTAG. I haven't yet tried programming the FPGA but hope to do that this evening. It has been a very busy month for me with not a lot of time for hobbies! My list for the next few weeks is:

1. Simple test program for FPGA that flashes the LEDs and tests clock provided by the Ethernet PHY.
2. Enable and update ethernet MAC so that device can be pinged. This will also be a separate test FPGA file.
3. Program clock block to multiply oscillator by 2 over I2C. At first this will be a standalone FPGA bit file to do just this one task. The settings on the clock block or nonvolatile so it needs to be executed just once.
4. Enable and test RX.
5. Enable and test TX and TX preamp.

I will post standalone FPGA bit files for steps 1-3 so that you can test also. By the time we are to step 4, pretty much the entire existing HL1.22 firmware will be ported. At that point it becomes a job of enhancing the firmware to better use the new capabilities. 

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

T2 needs to be installed.  I'll probably install T1 also for low power tests.

I have a USB Blaster inbound.

Stew

KF5KOG

[Steve Haynal]

Hi Stew,

The backside looks good too. May I use your photos in various places on the web? Your assembly looks much cleaner than mine.

Also, what assembly techniques (iron, skillet, hot air, oven, solder paste, etc.) did you use? I've been using mainly an iron, but some hot air. I would use more hot air if I can consistently apply solder paste to fine pitches without a stencil.

Finally, how much time did it take you to do this standard assembly? I estimate I am averaging 1 minute per pin, so 18 hours for a complete standard build, 13 hours if the main ICs are presoldered, less time for a no PA build.

[Steve Haynal]

Hi Group,

Here is an update on the HL2beta2 prototype testing and building. The LEDs, ethernet clock and FPGA eeprom are working. I've committed this first test (leds) to github. The gigabit ethernet interface is also working. I've committed a second test which is just the ethernet portion of the firmware. I can flood ping the unit without errors or speed/latency degradation. Flood ping is a good indicator that the interface is healthy. A working ethernet interface is a major hurdle and worry of mine to complete for a functional HL2. Now the two potential killers to the prototype that I worry about are problems with the AD9866 clock, although there are workarounds if the the Versa clock is not functioning, and noise/EMI issues, especially with the new power supply. Next, I will try to program the Versa5 clock generator to generate 76.8 MHz from the 38.4 MHz oscillator.

[kf5kog]

Hi Steve,

Feel free to use pictures as you wish.

I used and Iron for all of the assembly.  I tried using solder paste and hot air for the IC bottom pads but found it was just as easy heat up the PCB ground pad with iron then touch the chip pad and apply solder.  You could see the solder flow and come back out the little vias around the large hole.  Not sure exactly how long to build but I think 15-18 hours is about right.  Some of the time spent finding and verifying components in Kicad/PCB and schematic.  Once some kind of component placement guide is available, a few hours can be shaved off.   This is my first time with 0603 parts but not with IC's like the Cyclone.

73, Stew

KF5KOG

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[Stew KF5KOG]

Steve,

I'm ready to try the LED firmware test.   Do I only need to load the jic file?

One thing that is odd, looking at my amp meter.  The meter is fluctuating between 280-300ma.  Looks to be about a .5 sec cycle

73, Stew

KF5KOG

[Steve Haynal]

Hi Stew,

Yes, please use the .jic file as it will confirm if your EEPROM can be programmed. After programming, power cycle the unit and you should see two LEDs on and two off. If the ethernet clock is working, the LEDs will count (inverted values) at a slow speed. The period of the fastest LED will be a few seconds. There is also the .sof file to test the ethernet. There is no .jic for ethernet in githb so this one is volatile and will not survive a power cycle. DHCP is enabled and the unit should connect to your network. You can check your router to see what IP address was assigned and even give it a static IP based on the MAC. You should then be able to ping the unit.

73,

Steve

KF7O

[Steve Haynal]

Hi Stew,

I am away from my unit but will check the current draw later.

73,

Steve

KF7O

[kf5kog]

Thanks Steve,  

I'll give it a go tomorrow.  

Stew

KF5KOG

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[Steve Haynal]

Hi All,

I've started capturing all immediate problems and to-do items for HL2 on the github issues list:

https://github.com/softerhardware/Hermes-Lite2/issues

Please feel free to add to this list, comment or even fix some issues. You only need a github account to post to this issues list.

73,

Steve

KF7O

On Thursday, December 29, 2016 at 6:42:59 PM UTC-8, Stew KF5KOG wrote:

Thanks Steve,  

I'll give it a go tomorrow.  

Stew

KF5KOG

[Stew KF5KOG]

Hi Steve and group,

When I loaded the LED .jic file my current dropped to a steady 100ma.  The LED test worked fine.

For the Ethernet test I was not able to see the HLV2 on the network.  One upper and one lower LED are now on steady. I can also confirm the ethernet LED's are very dim as you mentioned on the issues web page.  I think I may have an issue with my Gigabit LAN which is a mixed environment.  I also just found out that my computer is not gigabit ready which I assume will be a no go for operating the HLV2.  I have one PCI slot available on MB, I hope the bus speed it OK to support the HLV2.  What do you think before I order a network card.  Otherwise it may be time to upgrade my motherboard, been thinking of it anyways.

73, Stew

KF5KOG

[Glenn P]

Steve
what length case is the V2 PCB made to fit?  What length is the V2 PCB?  I notice that some parts (connectors)  on Stews board stick out from the edge of the PCB. I assume then they will go through the end plates of the case and end up 'flush'.

glenn
vk3pe

[Stew KF5KOG]

Hi Glenn,

PCB is about 94mm wide by 100mm using a ruler if you break off the tabs.  It will fit inside the cases advertised as 100x100mm, I have one. The inside PCB track is 94.9mm wide.   Otherwise it measures 100x100mm with the tabs.   The connectors will go through front and back plates.

Stew

KF5KOG

[Glenn P]

Thanks Stew for the info. Understood.

glenn
vk3pe

[Steve Haynal]

Hi Stew,

If your computer has USB2.0 or USB3.0, you might consider an inexpensive gigabit to USB adapter. These will work with the HL2 although you won't see as much bandwidth as with a native gigabit interface. The longterm plan is still to support both 100Mb and 1Gb selected by a jumper or firmware.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Several people have added comments to the issues on GitHub. Thanks! Hopefully this is a better way to track issues and problems with HL2 than threads on this list.

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

Thanks for the tip.  I had no idea those were available.

I have a question to make sure I loaded the firmware correctly, programming is not my strongest area.  Do I need to uninstall the LED firmware before loading the ethernet test firmware?  I didn't see an option for erasing.  Box was not checkable.

73, Stew

KF5KOG

[Steve Haynal]

Hi Stew,

Sorry for the late reply. No, you do not need to uninstall. Every time you program a .jic file, it overwrites the entire contents of the EEPROM with the new firmware.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

Sorry, but there was little progress this week. My family and I were traveling on holiday. Hopefully I will program the Versa5 clock generator this weekend.

73,

Steve

KF7O

[Stew KF5KOG]

No worries Steve, Family time is important.  My question was about the .SOF files.  Do they overwrite also, or is it installed along side of .jic?  When I power cycle after loading ethernet .sof , it reverts back to the LED test. I'm just wondering if I'm doing it right.

73, Stew

KF5KOG

[Steve Haynal]

Hi Stew,

Yes, that is correct. FPGAs have many LUTs (lookup tables) which must be configured to implement the desired logic. These LUTs are like RAM memory and lose there configuration when power is removed. On power up, the FPGA always programs itself from the EEPROM, and hence you see the LED test as that is what you programmed into the EEPROM at one point via the .jic file. When you program a .sof file, it bypasses the EEPROM and directly writes to the LUTs on the FPGA. This configuration is lost when power is removed.

73,

Steve

KF7O

[Stew KF5KOG]

crystal clear now!  Thanks   Stew KF5KOG

[Steve Haynal]

Hi Group,

The Versa5 clock generator is programmed and generating the target 76.8 MHz. The clock looks clean on my scope. To learn how to program the Versa5 at a low level, I dug out my Raspberry PI as it has easy to use I2C master capabilities. I connected the Raspberry PI's I2C interface to DB1 on the HL2 so that I could talk to the Versa5 directly. Python includes the SMBus modules which makes it easy to interactively use I2C. With input from Timing Commander and the VersaClock 5 programming guide, I figured out what registers to program and what values to use to set the correct output frequency. There are many features on the Versa5 and further tweaking may be beneficial. Once I understood how to program the Versa5, I decided to use this Verilog I2C interface for programming from the FPGA. Please take a look at this project as it is a good example of a well written, tested and documented open source RTL IP. I would like to evolve the HL2 to look more like this project. It exhibits the following good traits:

• Test benches using MyHDL (Python) and Icarus Verilog are included. One can simulate pieces of the design and look at waveforms with GTKWave, all open source tools.
  
• The design is very modular and uses standard interfaces. There is the I2C master module which can be connected to a wishbone interface, standalone init master or axi stream interface. I am using the standalone initialization master for now, but will eventually switch to the wishbone bus.
• All code is clean, concise, well organized and self documenting.

I have committed tests for the Versa5 clock into the Hermes-Lite2 git repository. Python tests for testing from the Raspberry PI are in firmware/tests/clock/pi. There is an FPGA bitfile firmware/tests/clock/bitfiles/top.sof to test from the FPGA. Once this bitfile is downloaded to the FPGA, one should measure a 76.8 MHz clock on the pin of J22 with the long trace. J22 is on the bottom side. To be careful, J22 should not be stuffed with a jumper until firmware that correctly programs the Versa5 is installed. By default, the Versa5 will generate a x4 clock. I am worried that this default will overclock the AD9866 and generate excessive heat in the AD9866. It is possible to permanently program the Versa5, although you have only one shot at this. Even after permanently programming the Versa5, you can still change everything dynamically over the I2C. I haven't yet tried the one time programming as I want to be sure I have the best settings picked. This will require repeating some phase noise experiments with the receiver.

I am on track to bring RX up and begin testing RX hopefully next weekend.

[Gilbert Cross]

> Hi Group, I just got around to painting my H-L V1 transceiver and
> decided to add some graphics, Likely will redo the Hermes
> figure(yellow toner ran). Soon hope to convert to a VNA.

Gil K8EAG

[Steve Haynal]

Hi Group,

Nice job on the graphics and painting Gil!

I finished an alpha version of the Hermes-Lite2 firmware with radio components this weekend.  I can connect to the Hermes-Lite2 with software but see little to no signal. I only just tried receive and haven't spent time debugging. I'm out of time this weekend but hopefully will debug it during the week. 

73,

Steve

KF7O

[Alan Hopper]

Steve,

this is all sounding very exciting and positive.  If I can provide any debug help from the software end please shout.  I've found the adc histogram in the later versions of my code a useful sanity check for my simple firmware experiments.  

I'm interested in any construction errors/faults that could be diagnosed from software, so if you or any other builder finds something that might be detectable from a sw test do mention it.

73 Alan M0NNB  

[Steve Haynal]

Hi Alan and Group,

Yes, I will definitely use your ADC histogram to fine-tune and verify ADC samples.

It turns out that I forgot to stuff B81 so the antenna was never connected. After fixing that, the receiver is working as expected. I like to connect a dummy load and increase the LNA gain to +40 dB as a simple test to look for noise introduced by the system. I do see some noise from the switching regulators at around 900 kHz as expected and the digital clocks (I think), but overall there are fewer birdies/noise hash and of lower amplitude than what I see with the same test on a HL1.22. This is also with a first pass of part selection and values for the switching regulator discretes, so their noise can probably be reduced further with some component tweaking. Also, I am running the switching regulators with their default internal frequency of around 900 kHz and haven't tried the FPGA-produced and controlled clocks yet. Overall, I am pretty happy as these artifacts will most likely have no effect with typical background noise and LNA gain levels.

Hopefully TX (just with preamp) will be running this weekend!

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

The initial firmware RTL for the HL2 with working RX is on github. This is *very* alpha code with some hardwired resets, missing clocks and bad timing. It is not ready for anyone to add to it.

Stew, the .sof and .jic bitfiles are there if you want to test you build on RX.

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

I seem to be still having LAN issues.  Or possibly hardware issue with the HLV2 ethernet.

My computer hardware has been upgraded which includes 1G ethernet port.  My router (Arris TG862G Time Warner Modem) is 1G capable.  One question that seems elusive when searching the internet is LED status definitions.  What is a 1G connection?  Green LED? Or amber?  There is also some confusion between left and right LED, even on my equipment there doesn't seem to be a standard.  From what I understand once the connection is made the LED that remains steady is the connection speed and typically on the right, Is this correct?  

With the latest firmware loaded, HLV2 All 4 LED's are on and red for the HL board

HL Ethernet LED's;  Yellow/Amber on the right and flashing green on left.  This appears to be failed connection indication.

I'll keep looking for HL hardware issues in the mean time.

Stew

KF5KOG

[Steve Haynal]

Hi Stew,

For my gigabit switch (TL-SG108), I see a solid green LED for a 1G connection. This LED will flicker when there is data on that port. Lower speeds use the amber LED, sometimes in combination with the green for either 10 or 100 Mbs. The green LED is on the left for me.

On the HL2, I'd expect only two LEDs on for the last firmware. The other two indicate clip conditions for the AD9866. Did you connect the clock via J22?

73,

Steve

KF7O

[Stew KF5KOG]

Well, I may have a 1G LAN issue.  The LED that is flashing is amber on all the connected peripherals, the other LED is steady green.  My computer shows both LED Amber, the NIC is hard selected to 1G.

I do not have J22 installed, I'll do that.

Stew

KF5KOG

[Stew KF5KOG]

With J22 installed I get no red LEDs.  I assume this is because of network connectivity?

Stew

KF5KOG

[Stew KF5KOG]

Update,  I did not notice before but lower left LED is flashing red.  I have not figured out the pattern yet.  couple of blinks then 4 or 5 blinks.  This is looking at edge with ethernet and FPGA on top.

Stew

[Steve Haynal]

Hi Stew,

This will most likely change, but for the firmware you are using, the LEDs are as follows:

D2:(your lower left) Packet detected to this device's MAC

D3: Software is connected and unit is running

D4,D5: ADC is clipping

When I turn my unit on, all the LEDs will flash once briefly. Then, after 5 to 8 seconds I see D2 flash indicating it has received a packet as part of the DHCP process. Sometimes I see another flash 5 to 8 seconds after that. If I ping the unit (I get the IP address that was assigned directly from my router), then D2 will flash every time it receives a packet. Once I connect software, both D3 (run) and D2 (many packets now) are always on. Regarding the LEDs on the HL2's ethernet connector, the orange LED will be on solid and the green LED will blink along with any network activity.

I suspect DHCP is not working for you. There were some recent changes to DHCP for renewal that may have altered normal behavior, and DHCP has always been problematic. Are you comfortable using WireShark? The best way to debug is to provide a WireShark dump of the DHCP interactions. Do you have other gigabit devices which are succesfully using DHCP on your network? If DHCP fails, an APIPA is assigned: 169.254.34.221 (I think). You can configure your network to reach that. Also, I changed some clock frequencies so some of the timeout periods in DHCP may have become too short. In the past we needed very long timeout periods to work with some routers. I will check that and let you know. What is your local subnet? In the worse case, we build the RTL with a fixed IP just to see if DHCP is the problem.

[Stew KF5KOG]

Hi Steve,

I get the same all for LEDs on power up.  D2 blinking is a good thing, packets getting through.  I agree it's a DHCP issue.

I'll need to check for sure in the morning, but I believe the subnet is 255.255.255.0 with standard 192.168.0.* addresses.  As far as a giga byte device I have none that require it but are capable, other computers, xbox 1(hard wired) and several other devices.  While trying to get this all worked out all I had connected was the shack computer(win7 Pro) and the HLV2. into my router.  I never used wireshark, just downloaded it and will give it a try.

Stew

KF5KOG

[Steve Haynal]

Hi Stew,

I didn't see anything wrong with the clock to the DHCP module or any of the recent changes to that RTL. I cancelled the lease and router-assigned IP in my home network and tested that the HL2 still gets an IP address via DHCP. I recompiled the RTL with a static IP and tested that it is working. I sent you a PM with HL2 firmware using a static IP. Please let us know how that goes.

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

I got the jig file. Thank You.  I will give it a try tonight.   I've also been playing with Wire shark, I have it working to catch DHCP traffic.

Stew

KF5KOG

[James Ahlstrom]

Hello Steve,

I looked at the DHCP code in Hermes-Lite2, and it should work for the initial DHCP request for an IP address on power up.  There are no known issues with this code.  There are issues with DHCP renewal, and I am working with Phil to fix them.  I will keep you posted.

Jim

N2ADR

[Stew KF5KOG]

Hi Steve,

Loaded that static IP .jig, ping worked then connected to powersdr first try!

Now I need to build the RX transformer.

Thanks Steve!

Stew

KF5KOG

[Steve Haynal]

Hi Stew,

That sounds good. Either there is an incompatibility with the HL2 and your DHCP server, or DHCP is not working at gigabit speeds on your home network. Can you capture and send a Wireshark dump of the DHCP negotiation attempt using the first firmware on your network? Are other devices able to obtain an address via DHCP on your network at gigabit speeds? No rush, but it would be nice to solve this problem in the next few weeks before others have HL2s.

73,

Steve

KF7O

[Steve Haynal]

Hi Jim,

I've had no issues with DHCP on the HL2. The RTL looks very clean to me, cleaner than it used to be now that it has the 1,2,4 second retries. I haven't tested renewal closely yet. I've been power cycling the unit before the lease expires as I am frequently updating the firmware. I will let you know if I see any problems with renewal. 

Stew is having problems with the initial DHCP IP address request. Hopefully he can provide a Wireshark capture.

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

I will have time on Monday to send a wireshark dump.

I have the network card in my desktop manually set to gigabit instead of auto sense in device manager.  I assume it is requesting gigabit speeds and is successful.

At least I know it is my LAN instead of a hardware issue.

Stew

KF5KOG

[David Jones - KB9GPM]

For what it's worth. I've seen auto negotiation problems in the past with different hardware vendors.  If I remember right, the equipment would get into a kind of race condition trying to match each other.  Not sure that is what is going on here.  But it might be food for thought.

David

   KB9GPM

[Steve Haynal]

Hi Stew and David,

Maybe we need to start keeping a list on the wiki of good/bad DHCP servers. There are so many different routers out in the wild and not all implement DHCP in the same way or precisely follow the spec.

I always buy routers that support open source firmware such as Tomato. Currently I am running Tomato by Shibby. This firmware adds the features you'd find on a $200+ router to a $50 router. The router is essentially running Linux and I can ssh to it, run capture programs for Wireshark to see all sides of a DHCP conversation, mount file systems, etc. I've never had problems with DHCP on routers running Tomato. One recommendation is to buy a router that will run Tomato.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

This weekend I brought the low power TX output up. At first I was seeing garbage on my scope. The HL2 board has better timing due to shorter trace lengths on the PCB and I had to adjust the timing of the digital output to the the TX DAC. This channel is running at 2x the speed, so 153.6 MHz, and can be a bit tricky. After that change, I see a clean signal on my scope. I feel that it is cleaner than the older HL but I still need to run spectrum analysis. I hope to post a spectrum plot later this week. Also, with a clock of 76.8 MHz, there are some levels that need to be adjusted on the TX DSP path. The signal is distorted if the input audio levels are more than 0.85 of max. This is something I've known about and just have to get around to fixing, hopefully this week.

 I'm on track to bring up the full PA next weekend.

[James Ahlstrom]

Hello Steve,

I have no issues with DHCP either, despite a very tardy response from my DHCP server.  I look forward to a WireShark capture from Stew.

The current DHCP renewal code blocks the samples UDP traffic starting from the Request until the server responds with the ACK and a renewed lease.  This is not satisfactory, especially if the ACK is delayed.  I sent new code to Phil to enable UDP to continue during renewal.  He is testing it.  When everything works, we will want to use this new code.

Jim

N2ADR

[kf5kog]

Hi Jim and all,

I sent file to Steve via PM, but I'll share it here.  This is my first time using wire shark so I'm not sure if I did it right.  I started the capture with HLV2 powered off and then powered the radio within a few seconds.  Wire Shark was run from my shack computer and not captured from the router directly.  The computer ip is 192.168.0.5.  The router is an Arris TG862G.  The HLV2 and my computer are directly connect to router.  I have another wireless router, which is actually a switch now, connected to the Arris router which feeds the rest of my home LAN.

Stew

KF5KOG

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[Dani EA4GPZ]

El 23/01/17 a las 08:10, Steve Haynal escribió:

> I always buy routers that support open source firmware such as Tomato

> <https://advancedtomato.com/>. Currently I am running Tomato by Shibby.

> This firmware adds the features you'd find on a $200+ router to a $50
> router. The router is essentially running Linux and I can ssh to it, run
> capture programs for Wireshark to see all sides of a DHCP conversation,
> mount file systems, etc. I've never had problems with DHCP on routers
> running Tomato. One recommendation is to buy a router that will run Tomato.

Hi all,

Another open-source firmware that you can use is OpenWRT (essentially
another Linux distribution targetting routers, just as Tomato). It
supports a lot of different routers (from a first glance it seems that
Tomato only supports Broadcom chipsets). I use OpenWRT in all my routers
at home and I'm very happy with it. I also use it for Hamnet routers.

There's also DD-WRT, but I don't have any experience with that.

73,

Dani EA4GPZ.

[Steve Haynal]

Hi Stew,

I also sent your capture file directly to Jim. He says he sees only half the conversation but does see the HL2 send Discover and Request DHCP packets. This means that your DHCP server is communicating and probably did send a DHCP Acknowledgement (Ack) but the HL2 didn't decode it properly so dropped the whole DHCP process. Assuming this is correct, I took a deep look at the HL2 Ack code and noticed two suspicious behaviors. For background, an Ack ends with a list of options. The RFC 2132 specification does not guarantee what options will exist or in what order they will appear. This is a place where the current HL2 DHCP code may be weak. First, the code assumes that option 53 (DHCP message type) always comes first. This is probably a safe assumption 99.9% of the time, but since it is not guaranteed by RFC 2132, I updated the RTL to handle any order of options, including option 53. Second, RFC 2132 defines a single octet pad option used to align words. This was not properly supported in the RTL so I added support. I suspect this might be the culprit and may even be causing problems for renewal where a different set of options may be seen. I verified that these changes work for me and sent a new .jic file to Stew for testing.

73,

Steve

KF7O

On Monday, January 23, 2017 at 10:42:56 AM UTC-8, Stew KF5KOG wrote:

Hi Jim and all,

I sent file to Steve via PM, but I'll share it here.  This is my first time using wire shark so I'm not sure if I did it right.  I started the capture with HLV2 powered off and then powered the radio within a few seconds.  Wire Shark was run from my shack computer and not captured from the router directly.  The computer ip is 192.168.0.5.  The router is an Arris TG862G.  The HLV2 and my computer are directly connect to router.  I have another wireless router, which is actually a switch now, connected to the Arris router which feeds the rest of my home LAN.

Stew

KF5KOG

[Steve Haynal]

Hi Dani,

I've used both OpenWRT and DD-WRT in the past. They are both very capable but I've found Tomato easier to use, especially for a novice. Unfortunately, as you point out, Tomato runs only on a Broadcom chipset. I only purchase a router if it will run Tomato.  

Jim pointed out that you can also use a managed switch and mirror a port to see both sides of a DHCP conversation. Both my gigabit switches are unmanaged, so I can't try. That should also be possible on an openWRT/DD-WRT/Tomato router where you turn of the internal DHCP server and mirror ports or capture directly to the router. 

73,

Steve

KF7O

[Stew KF5KOG]

Hi Steve,

That firmware worked and connects to PowerSDR!  The right upper and lower LEDs are on.  The strange thing is that I do not see the device connected to my router.  Client list has been refreshed.  I also tried pinging the address that shows up in PowerSDR and ping fails.  Interesting.

With your original firmware I would first look for the the device then I would try and connect Powersdr even if I didn't see the device in my router list just as I did this time.

Attached is the Router client list and PowerSDR Hardware config page.

Stew

KF5KOG

[Stew KF5KOG]

Error in my last message, Left upper and lower LEDs are on after Powersdr connects.  What was I thinking..hihi

Stew

[Stew KF5KOG]

Group,

I have done some RX testing.  Attached my signal generator and was able to calibrate frequency and signal level.  Connected to antenna I can receive signals but I get ADC overload message.  I know this is just beta firmware but I am happy the hardware appears to be working!

Stew

KF5KOG

On Saturday, November 26, 2016 at 9:06:41 PM UTC-5, Steve Haynal wrote:

Hi Group,

To facilitate the Hermes-Lite 2.0, I've made the following online changes:

• There is now one web site with links to everything Hermes-Lite related: http://www.hermeslite.com
  This site is very simple for now but may grow in the future. 
  
• A new github repository, Hermes-Lite2, has been setup and is linked from www.hermeslite.com. All Hermes-Lite 2.x development will be here. The old repository remains for 1.x.
• There is a new Hermes-Lite 2.0beta2 Block Diagram also linked from the main site.
• There is a Hermes-Lite 2.0 Development Gallery with pictures of and comments on the new PCBs now in hand. Again, this is linked from the main site. 

Is there anyone with graphical art experience on this list? I'd love to have a logo for the Hermes-Lite. Perhaps tiny shoes with wings or something else that alludes to Hermes and Lite.

73,

Steve

KF7O

[Steve Haynal]

Hi Stew,

Glad it is working with DHCP but it is strange that the client is not showing up. The address is 192.168.0.15 and at the end of the list. Is there a second page of clients? If you disconnect and remove some other client, does the HL2 show up?

I just tried to ping the HL2 with this firmware and I can't either. I occasionally see the error below. I often see errors like this when I've introduced some timing path into the RTL. The changes I made really added quite a bit of logic to one state. I will go back and write that differently to see if I can improve the timing and bring back ping. A timing path like this might also impact ARP and cause the device not to show up on your client list.

Warning: time of day goes back (-102795573640409566us), taking countermeasures.

64 bytes from 192.168.33.248: icmp_seq=258 ttl=128 time=0.000 ms (DUP!)

wrong data byte #16 should be 0x10 but was 0x0

#16 0 10 13 12 15 14 17 16 13 19 1b 1a 1f 1c 1f 1e 3b 21 23 22 27 24 27 26 23 29 2b 2a 2f 2c 2f 2e 

#48 2b 30 33 33 37 34 37 36

73,

Steve

KF7O

[Steve Haynal]

Hi Stew,

Can you also try other software, for example Allan's SparkSDR software or Jim's Quisk. They both run on Windows. I ran SparkSDR overnight with this firmware and saw no problems.

73,

Steve

KF7O

[Steve Haynal]

Hi Stew,

FB on RX. Regarding the overload, at what gain setting do you start seeing the ADC overload? The PowerSDR LNA gain setting table on this wiki page should apply. Also, do you have an HL1? If so, how does it compare regarding ADC clipping? Can you please try Quisk and SparkSDR and report if they clip too? I actually haven't tried PowerSDR with the HL2 yet. Finally, what RX balun did you end up using? Is it 14 turns on AD9866 side to 5 turns on Antenna side as described here? Or is the commercial RX balun used on Jim 1.42 board? Either should work fine by the way.

On the HL2, are both overload leds lit, or just one? With full connection and overload on both high and low swings, all 4 leds will be lit. If it is just one overload led lit, you should check that input is reaching both sides of the AD9866 differential input. For example, one of the enamel coated wires on your RX balun may not be electrically connected.

73,

Steve

KF7O 

[Stew KF5KOG]

Hi Steve,

Powersdr was a fresh install so I didn't have it configured completely.  With Dither/Random and S-ATT setup I do not get ADC1 Overload message! Even at 0db attenuation.  Both R/H LEDs are off now.

For the balun I'm using a coilcraft form the V1.32 front end.  Not of sure the exact part number.

Spark SDR seems to work fine, but I don't have a lot of experience with it.  I will try Quisk in a while.

As far as my router DHCP list, I do not see another page.  I'll try what you suggested. 

Stew

KF5KOG

[Alan Hopper]

Steve, Stew, Jim,

great progress, congratulations.

Jim, as you are looking at the ethernet code for both HL2 and HPSDR I thought I'd mention a couple of things I noticed in playing with the new protocol code on an Orion.  I have mentioned all this to Phil and it all may be fixed by now.  On long tests my software would stop receiving data but the radio would appear to still be sending it elsewhere on the network, I guessed this was DHCP or some other packet causing the radio to send to a different destination.  Sending discovery packets from a different pc or port also caused the data to be redirected, I think this was fixed in the HL firmware at some point.  My software currently relies on packets from the radio to trigger sending packets back so once the radio starts sending to the wrong place all communication stops.  I tested with a timeout to send packets and this makes it recover i.e. the radio starts sending to the correct place on receiving a packet.  This may mean some software covers up this type of fault.  

73 Alan  

[Stew KF5KOG]

Hi Steve,

I disconnected all devices from my network and the HL2 doesn't show up on DHCP list.  It certainly is getting the IP address, different ones at times after being off for a while.  I have an open source wireless router due in today.  Hope to have some time to set up Tomato tomorrow.  Maybe different results?  We'll see.

Stew

KF5KOG

[in3otd]

Hello,
I've started assembling my board, did the whole bottom side, since I wanted to use solder paste and a hot plate, hoping to gain some time. Results were not too bad but not perfect either: in general I used too much solder paste and had some shorts here and there.
Then I did the "top-right" corner, where the DC/DC converters are. This one also with solder paste and a hot plate, since I temporarily left out C15/C18/C24 and C34 from the bottom to be able to place that corner on the hot plate. Reflow of this part went well, just needed to touch up a couple of solder joints for C20/C22/L2 which did not completely reflow, as I did not dare to leave the board on the hot plate for too long, hi.
I've tested the DC/DC converters, they all work fine. While I was at it, I've measured their efficiency w.r.t. the output current, so I can show the customary graph

The 1.2 V converter efficiency is maybe a bit low but likely ok anyway. Tried all the regulators at the max current (one at a time), they get barely warm, the 1.2 V slightly more than the others. Even at full load the output voltage practically does not drop, output ripple is also low.

73 de Claudio, IN3OTD / DK1CG

On Thursday, December 15, 2016 at 6:21:32 PM UTC+1, Steve Haynal wrote:

Hi Group,

Stu and I have had an interesting private thread I wanted to share with the list. Stu added on some Hermes-Lite v2beta2 boards to another PCB order of his and has bravely decided to build one up even though there may still be some fatal flaws. Thanks Stu for taking this risk! You additional results will be helpful.

73,

Steve

KF7O

---------
Date: Thu, Dec 15, 2016 at 1:02 AM
Subject: Re: Hermes-Lite 2.0 Updates
To: Steve Haynal <st...@softerhardware.com>

Hi Steve, thanks for the info. I'll keep pushing forward with assembly.   OK to share this thread.

Stew

KF5KOG

On Dec 15, 2016 2:34 AM, "Steve Haynal" wrote:

Hi Stu,

Looks good! May I share this thread with the list? It is probably okay to assemble everything you like, but be sure to test for power supply shorts before powering it up. You could also check that the FPGA is alive. Make sure all the bypass and bulk capacitors are installed (schematic "Power" page for the FPGA) as well as R2,R3,R4,R5,R6,R7 and then see if you can detect the FPGA with Quartus and a programmer connected to CN1. 

I would leave off J22 until the clock is programmed to the proper frequency to avoid overclocking the AD9866.

The serial EERPOM for the FPGA (U1) is a wide body variant on the BOM (5.3mm) but the footprint is 3.9mm. I've ordered a couple of replacements. 

The firmware will need some changes to work with this board. One clock is now provided by the ethernet PHY. This is how it was done on the Hermes but not on the CVA9. The ethernet PHY device select address has changed. The clock will need to be programmed. This will probably be done via CN1 at first. Also the biasing levels must be set. Again, this will be a one time setting done over CN1 at first. Eventually the clock and bias will be accessible to software in the firmware.

73,

Steve

KF7O

On Wed, Dec 14, 2016 at 12:40 PM, kf5kog < wrote:

Hi Steve,

I have been working on mine too.  I ran into a problem with one of the ST1S10 regulators (1.2v)  It initially was working with resistors swapped.  As I was fiddling with the 3.3V reg to get it working the 1.2V reg stopped working.  As it turned out pin 7 apparently shorted out or nearly so at 75 ohms to ground pin 8.  Not sure what happened.  It may have been too much heat soldering bottom pad or not a good enough contact.  Replaced it today and all is good.  I've installed the difficult IC's too. Came out pretty good!

Is it OK to assemble it completely?  or is there a stage I should stop at awaiting the firmware?

I picked up some RD00HHS1 for the PA figured I'd give it a try on the HLV2.   Been doing some testing on the BX-202 1W amp with 10mw drive from Germany that uses them in a push pull configuration.  IMD results are very impressive.  I attached the article.  They are very cheap too!

73, Stew

KF5KOG

On Tue, Dec 13, 2016 at 1:33 AM, Steve Haynal  wrote:

Hi Group,

Here is the weekly update on my Hermes-Lite 2.0 prototype building progress. The FPGA on my handbuilt unit is alive and communicating over JTAG! This is the one with an FPGA from China that is a second-hand pull and was shipped without ESD packaging. There may still be undiscovered problems with specific IO banks or other pins. At first the nSTATUS pin never went high. This can be due to not all power supply pins connected. I borrowed a stereoscopic microscope and used an xacto knife to nudge each pin and determine if it was firmly soldered. I found ~10% of the pins were not well soldered. They were not flush with the PCB and instead were slightly raised, I suspect since this was a pulled part. After resoldering those pins, the board started to communicate over JTAG.

Today I also picked up the board from ZelPro with the 6 hardest ICs assembled. The difference between my soldering work on the handbuilt unit and their work is night and day. I will switch focus and complete the ZelPro assembled unit first. Hopefully I will be pinging the unit sometime this weekend.

73,

Steve

KF7O

 

 

On Monday, December 5, 2016 at 10:01:40 PM UTC-8, Steve Haynal wrote:

ZelPro just came back with $73 for 6 ICs assembled, no capacitors. I plan to drop of the parts tomorrow.

73,

Steve

KF7O

On Monday, December 5, 2016 at 9:59:09 PM UTC-8, Steve Haynal wrote:

Hi Group,

Here is an update on HL2beta2 prototype building progress. I completed the 1.2V, 2.5V and 3.3V power supplies and all looks good. This is enough to power everything except the RF preamp and PA. ZelPro returned with a quote, but for 6 ICs and 114 capacitors, they want $250 hand assembled or $90+$200 for reflow and a stencil. This is more than I anticipated. I've asked how much it will cost if the capacitors are left off as I am pretty comfortable and fast with those. I have started a 100% hand assembled by me unit also. This one will use parts I purchased mostly from China, the new parts will be sent to ZelPro. After great pains and a reminder that I am not very good at SMD IC assembly, I managed to solder on a FPGA from China. This was a pull so the pins were not perfectly aligned or flat and without solder. The hardest part has been device positioning and keeping it in place with all pins aligned, whether I use hot air, skillet, reflow (toaster) oven or iron. It may not work. The next step is just to get enough on the board to see if the FPGA is alive and only continue if it is. 

The end of the year is a very busy time with major work releases, school functions and family holidays.

73,

Steve

KF7O

 

On Monday, November 28, 2016 at 10:48:08 PM UTC-8, Steve Haynal wrote:

Hi Group,

Tonight I built the 1.2V power supply as I had those parts on hand. I examined the PCBs carefully and saw that two out of five had shorts that had been fixed with small cuts on the PCB. Electrical test is included and it would seem they found a few shorts and fixed them. Claudio reported an unfixed short on one of the test PA boards. I'm not sure why that short was missed. You can see the mark from the electrical test on each of the pads. At first the power supply was producing 2.4V. The first mistake found is that the values of R14 and R15 on the schematic are swapped. R14 should be 10K, and R15 20K. After fixing that, I see a very clean 1.2V although I did not have much load.

The rest of the parts arrive this week. I plan to contact ZelPro Tuesday or Wednesday to arrange for them to do the hardest assembly work.

73,

Steve

KF7O

On Saturday, November 26, 2016 at 6:06:41 PM UTC-8, Steve Haynal wrote:

Hi Group,

To facilitate the Hermes-Lite 2.0, I've made the following online changes:

• There is now one web site with links to everything Hermes-Lite related: http://www.hermeslite.com
  This site is very simple for now but may grow in the future. 
  
• A new github repository, Hermes-Lite2, has been setup and is linked from www.hermeslite.com. All Hermes-Lite 2.x development will be here. The old repository remains for 1.x.
• There is a new Hermes-Lite 2.0beta2 Block Diagram also linked from the main site.
• There is a Hermes-Lite 2.0 Development Gallery with pictures of and comments on the new PCBs now in hand. Again, this is linked from the main site. 

Is there anyone with graphical art experience on this list? I'd love to have a logo for the Hermes-Lite. Perhaps tiny shoes with wings or something else that alludes to Hermes and Lite.

<softerh...@gmail.com>

73,

Steve

KF7O

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[Jack Generaux]

I just finished populating my board. First, I used hot air for the bottom parts, followed by hot air for the top but leaving off all the ICs except the regulators.  I checked the voltages and they are correct.  I had to short pin 1 and 2 of the 9 volts supply regulator to enable it,  I used a 16.2K and a 1.6K resistor pair and am getting 8.98 volts. I then installed the remailning ICs with a toaster over reflow I built. Spent about an hour with 10x loupe inspecting and using solder braid to touch up excess solder.  I just got the USB blaster in the mail this afternoon but too pooped to play with it any more tonight -- tomorrow.  

73,

Jack (W0FNQ)

[Steve Haynal]

Hi Claudio,

Thanks for the measurements! The efficiency for the 1.2V does look low. The datasheet does say what to expect for 12V in 1.2V out.

FB on the assembly. How are you applying the solder paste? I find this difficult for the smallest parts.

73,

Steve

KF7O

[Steve Haynal]

Hi Jack,

Thanks for the update. I just updated the wiki with a few more build notes.

73,

Steve

KF7O

[Jack Generaux]

Well, I screwed up.  I forgot to check for shorts between the 2.5 and 1.2 supplies after reflowing the ICs; it was fine before the reflow.   I applied power and started to flash but got error.  I then went back and discovered my screwup --  2.5 volts on the 1.2 lines.  I pulled the FPGA and the short went away, but I am guessing I toasted my FPGA and ethernet controller since the controller also uses the 1.2 supply.  I could try remounting the FPGA but don't want to keep subjecting the board to soldering and risk descruction when I suspect the damage is aready done.  Does this seem like the best path, or is there a chance the ICs are still good?

Jack(W0FNQ)

[Steve Haynal]

Hi Jack,

Sorry to hear about the shorted power supplies. We'll have to stress in the build notes to check the power supplies after any ICs are installed. I don't know of an easy way to check the ICs without having them installed on the board. They are pretty rugged and I wouldn't be surprised if they were still good as you had no activity during the time they were overpowered. My best guesstimate is that you have a 50/50 chance of them working.

73,

Steve

KF7O

[Jack Generaux]

Steve,

Well, after thoroughly cleaning the pad with braid and flux, I tacked the FPGA without any new solder; the short came back.  I guess whatever problem was there orginally caused the internal chip circuit to be permantly damaged.  I am at a loss of the original problem.  I inspected the connection wth 10x loupe and never did find an issue.  Although I use an antistatic workpad and the reflow temps looked good, perhaps I damaged the FPGA chip installing it.  I'll get new chips and try again.  Thank for the advice, Steve.

Jack

[in3otd]

Hello,
to apply the solder paste I use a small syringe with a 23 gauge needle that has been cut very short (bought from KD5SSJ several years ago). Usually I apply too little paste and cannot easily see the solder fillet even if the part is well soldered, so this time I decided to apply more but evidently that was too much.

I do not see an efficiency curve for 1.2 V out on the ST1S10 datasheet but just using the data for the internal FETs Rds_on there and the inductor resistance from its datasheet I get a theoretical efficiency of about 80 % at 1.5 A out, then other losses should be added to that.

I have now soldered down everything, had a curious issue with the Ethernet PHY which I'll describe later. My USB Blaster clone is apparently still on the boat from China, so looking around for an alternative solution I saw that the one on the BeMicro CV A9 can be used too; when a voltage is connected to the appropriate pin on the JTAG header there, the on-board programmer is switched from the on-board FPGA to the JTAG header.
From the first tests it seems that something is not right; most of the time I do not get the binary counter on the LEDs with the test .sof file; I could see that just once, usually I get just two LEDs on, steadily. Also I do not get any clock with the VersaClock .sof file. Now the fun part begins, hi.

73 de Claudio, IN3OTD / DK1CG

[Steve Haynal]

Hi Claudio, Jack and Group,

Jack, sorry about the damaged parts. 

Claudio, I meant to say the datasheet *doesn't* have what to expect for 12V in and 1.2V out. I need to read my posts before pressing the send button!

There was some bad soldering on a PA resistor that caused the big variation in Vgs for 100mA I reported earlier. After fixing that, I see much closer Vgs for both transistors and the values are also close to what Claudio reported. However, even though my transistors come from the same strip, the Vgs for 100mA for one is ~2.97 and the other ~2.92V. This is 4 ticks difference of the digital potentiometer. Currently the bias settings are hardcoded into my local firmware. I will probably hack changing bias settings in to free fields of the openHPSDR protocol for immediate use, but eventually replace this with memory mapped locations. I've started out conservative with 90mA bias and 3W output. I want to check this, especially thermal dissipation, before cranking up the power. As Claudio indicated earlier, it looks like we will have to add some attenuation with R94, R97, R98 and R100 as I am at 3W output when Quisk's spot is only set to 0.45. So far nothing is getting too hot after ~1 minute. I need an infrared temperature gun for better measurements. Below are spectrum plots of TX on 20M without and with a filter. The filter is a QRP Labs 20M small filter board that I've put inline with the coax and is not the best. Overall, everything still needs tweaking but at least the PA is showing signs of life.

No Filter:

Filter:

73,

Steve

KF7O

[Stew KF5KOG]

Hi All,

I started running WSPR using Spark SDR.  The HL2 low power output is connected to John's 5W amp.  My main concern was drift that affected V1.2, So far I do not see any drift!  This was 2 back to back transmits at 2 watts.  The radio was idle in RX for about 30 minutes prior to TX.  So I think the board was at a stable tempurature.  With V1.2 the first transmit would have drift in the -3 to -4 range, then with the second TX drift would stabilize.

Steve,  For filter selection, I see it is now done through I2C. Has this been implemented in the firmware yet?

Stew

KF5KOG

On Saturday, November 26, 2016 at 9:06:41 PM UTC-5, Steve Haynal wrote:

Hi Group,

To facilitate the Hermes-Lite 2.0, I've made the following online changes:

• There is now one web site with links to everything Hermes-Lite related: http://www.hermeslite.com
  This site is very simple for now but may grow in the future. 
  
• A new github repository, Hermes-Lite2, has been setup and is linked from www.hermeslite.com. All Hermes-Lite 2.x development will be here. The old repository remains for 1.x.
• There is a new Hermes-Lite 2.0beta2 Block Diagram also linked from the main site.
• There is a Hermes-Lite 2.0 Development Gallery with pictures of and comments on the new PCBs now in hand. Again, this is linked from the main site. 

Is there anyone with graphical art experience on this list? I'd love to have a logo for the Hermes-Lite. Perhaps tiny shoes with wings or something else that alludes to Hermes and Lite.

73,

Steve

KF7O

[Steve Haynal]

Hi Stew,

Thanks for testing drift. It is good to hear that the new oscillator and clock appear more stable. At 500 ppb, I haven't really had to calibrate the frequency. How calibrated is your unit?

I (KF7O) am one of the spotters on your list! This is the first Hermes-Lite2 to Hermes-Lite2 WSPR spot. What antenna are you using?

Yes, filter selection will be via I2C. It is not in the firmware yet. The i2c bus expander IC is planned for the filter board. To use the HL2 with other filters, you will need a MCP23008 or MCP23017 based i2c bus expander. For example this.

73,

Steve

KF7O

[Steve Haynal]

Hi Group,

The beta2 build notes located on the wiki at:

https://github.com/softerhardware/Hermes-Lite2/wiki/Build-Notes-2.0beta2

have been updated to include all that I have built so far. The notes are rough and will be refined over time. There is a picture showing how I mounted the relay and heat sinked the PA. See the QRP Power Amplifier section at the end.

73,

Steve

KF7O

[Alan Hopper]

Stew, Steve,

Congratulations on the Hermes-Lite2 to Hermes-Lite2  contact. It is very good news about the drift, hopefully I can throw away the unfinished drift compensation code I recently rediscovered!

73 Alan M0NNB

[Stew KF5KOG]

Hi Steve,

Wow, yes I see that now on WSPR!  Very cool.  I'm using an MFJ-1798 Verticle mounted 10 feet high.  Very happy with it.  I've taken it down 3 times to move the last few years and it survied the abuse well.    I was comncerned with how it would handle the ice storms up north.  So far so good!

Frequency cal was very close to dead on.  I did tweak it a little.

Thanks for the link to I2C expander.  I'll order one up.

Stew

KF5KOG

[Stew KF5KOG]

Hi Alan,

HL2 with be up on WSPR most of the day today.  I'll let you know how it work.  I do not know what the drift will be when using the on board PA, if any at all. 

Stew

KF5KOG

[Sid Boyce]

I believe a few people are looking at this board for using with the Pi3
based pihpsdr and a pihpsdr based on the ODROID-C2.
https://www.abelectronics.co.uk/p/54/IO-Pi-Plus

I have one of these dual-chip boards in addition to 2 MCP23017 chips to
add to the Pi3 and the -C2.

I am currently using HL 1.42 + JW's 5W PA with pihpsdr running on Pi 3
with Raspbian and ODROID-C2 with 64-bit Ubuntu 16.04.2 LTS, no GPIO
connections so far.

pihpsdr OC settings supplied by JW:-

160M - 1000001

80/75 - 0100001

60/40 - 0010001

30/20 - 0001001

17M - 0000101

15M - 0000011

12/10 - 0000000
73 ... Sid.

On 14/02/17 04:19, Steve Haynal wrote:
> Hi Stew,
>
> Thanks for testing drift. It is good to hear that the new oscillator
> and clock appear more stable. At 500 ppb, I haven't really had to
> calibrate the frequency. How calibrated is your unit?
>
> I (KF7O) am one of the spotters on your list! This is the first
> Hermes-Lite2 to Hermes-Lite2 WSPR spot. What antenna are you using?
>
> Yes, filter selection will be via I2C. It is not in the firmware yet.
> The i2c bus expander IC is planned for the filter board. To use the
> HL2 with other filters, you will need a MCP23008 or MCP23017 based i2c

> bus expander. For example this
> <https://www.aliexpress.com/item/Bidirectional-16-Bit-I-O-Expander-with-I2C-IIC-Serial-Interface-Module-MCP23017/32779407626.html?spm=2114.01010208.3.321.K2WKLm&ws_ab_test=searchweb0_0,searchweb201602_3_10065_10000073_10068_10501_10000074_10503_10000032_119_10000030_10000026_10000023_10000069_10000068_10060_10062_10056_10055_10000062_10054_10000063_10059_10099_10000020_10000013_10103_10102_10000016_10096_10000056_10000059_10052_10053_10107_10050_10106_10051_10000097_10000094_10000053_10000007_10000050_10084_10083_10000100_10080_10000047_10082_10081_10110_10111_10112_10113_10114_10115_10000041_10000044_10078_10079_10000038_10073_10000035_10122_10121-10503_10501,searchweb201603_2,afswitch_3,ppcSwitch_3,single_sort_3_default&btsid=c6370f87-b753-4df2-9dad-d21ef84bbe5b>.

>
> 73,
>
> Steve
> KF7O
>
>
> On Monday, February 13, 2017 at 12:07:41 PM UTC-8, Stew KF5KOG wrote:
>
> Hi All,
>

> I started running WSPR using Spark SDR. Â The HL2 low power output
> is connected to John's 5W amp. Â My main concern was drift that
> affected V1.2, So far I do not see any drift! Â This was 2 back to
> back transmits at 2 watts. Â The radio was idle in RX for about 30
> minutes prior to TX. Â So I think the board was at a stable
> tempurature. Â With V1.2 the first transmit would have drift in

> the -3 to -4 range, then with the second TX drift would stabilize.
>

> Steve, Â For filter selection, I see it is now done through I2C.

> Has this been implemented in the firmware yet?
>
> Stew
> KF5KOG
>
> On Saturday, November 26, 2016 at 9:06:41 PM UTC-5, Steve Haynal
> wrote:
>
> Hi Group,
>
> To facilitate the Hermes-Lite 2.0, I've made the following
> online changes:
>

> * There is now one web site with links to everything
> Hermes-Lite related: http://www.hermeslite.com
> This site is very simple for now but may grow in the future.Â
> * A new github repository, Hermes-Lite2, has been setup and
> is linked from www.hermeslite.com
> <http://www.hermeslite.com>. All Hermes-Lite 2.x

> development will be here. The old repository remains for 1.x.

> * There is a new Hermes-Lite 2.0beta2 Block Diagram
> <https://github.com/softerhardware/Hermes-Lite2/raw/master/hardware/hl/bd.pdf>Â also

> linked from the main site.

> * There is a Hermes-Lite 2.0 Development Gallery
> <https://github.com/softerhardware/Hermes-Lite2/wiki/Development-Gallery>Â with

> pictures of and comments on the new PCBs now in hand.

> Again, this is linked from the main site.Â

>
> Is there anyone with graphical art experience on this list?
> I'd love to have a logo for the Hermes-Lite. Perhaps tiny
> shoes with wings or something else that alludes to Hermes and
> Lite.
>
> 73,
>
> Steve
> KF7O
>

> --
> You received this message because you are subscribed to the Google
> Groups "Hermes-Lite" group.
> To unsubscribe from this group and stop receiving emails from it, send
> an email to hermes-lite...@googlegroups.com

> <mailto:hermes-lite...@googlegroups.com>.

> For more options, visit https://groups.google.com/d/optout.

--
Sid Boyce ... Hamradio License G3VBV, Licensed Private Pilot
Emeritus IBM/Amdahl Mainframes and Sun/Fujitsu Servers Tech Support
Senior Staff Specialist, Cricket Coach
Microsoft Windows Free Zone - Linux used for all Computing Tasks

[Steve Haynal]

Hi All,

I tried the first TX with the new PA this morning while 20M was open. No reported drift. Not too much heat. This was after the unit had been up all night but not transmitting. DL1HI spotted me, and then I spotted him next cycle. Contacting Europe is actually a bit difficult for me from the west coast over the magnetic north pole. Screenshots below.

73,

Steve

KF7O

[Alan Hopper]

Steve, Stew,

that is a great result with no drift with the on board amp, very annoyingly I missed Steve's transmission as I accidentally turned off my radio, I did spot Stew and detected no drift.

73 Alan M0NNB

[Stew KF5KOG]

Indeed, that is good news Steve!

Alan, again I really like your software.  I just completed a clean install of Win 7 on my laptop.  Got HL2 up and running in no time with your software!  Install WSPR, WSJT, visual C, Spark SDR. Open program, enter call sign and locator.....on the air! Too easy!

I attached is my temporary set up.  

Stew

KF5KOG

[in3otd]

 ...I really need to switch to Windows and finally try Alan' SW here, hi.

Nice setup, Stew, I'm slowly trying to catch up here; my H-Lv2b2 is working now, main issues were a few bad solder joints around the Ethernet PHY and that I forgot to solder R42, so the output from the VersaClock was not going anywhere.

I'll leave the H-Lv2 in RX on the 40 m band in WSPR for a while to check.

[Steve Haynal]

Hi Claudio,

Glad to hear that your HL2b2 is working now.

73,

Steve

KF7O

[in3otd]

Hello,
I see I spotted Stew a few times this night on 40 m; I was hoping to be able to spot Steve too but it seems that the west coast is too difficult from here.
In the morning I changed to 20 m but the propagation seemed not that good.

Stew, are you using some additional heat sink for the board? I have added a small fan near the board, since without it the AD9866 gets quite warm - I can keep a finger on it for a few seconds at most. I think its ground pad is soldered correctly, the bottom side seems to have nearly the same temperature.

Regarding the curious issue with the Ethernet PHY I mentioned the other day, I don't think it will happen to other builders, but it's a nice example of Murphy's law at work... I soldered the Ethernet PHY (and most of the other fine-pitch ICs) using drag-soldering. After inspecting the IC I saw there was a short between a few pins, on the side near the card border. Nothing surprising, I just added some flux and tried to remove the short, but the solder bridge between the pins remained there. So I took a fine desoldering braid and removed practically all solder on the pins and pads. But the short was still there: looking with a loupe, it was now clear that there was something *under* the pins which was shorting them. Then I realized that the pad for pin 43 (unconnected) was no longer there. Apparently during the drag soldering attempts I heated up that unconnected pad too much and pushed it *under* the nearby pins. It took quite some patience and a few attempts with a needle to remove that loose pad from there.

73 de Claudio, IN3OTD / DK1CG

[Jack Generaux]

Its alive!  Got new FPGA installed and it passes the LED, Ethernet, and Clock tests.  Will finish installing receiver pieces and more testing tomorrow.

Jack (W0FNQ)

[Stew KF5KOG]

Hi Claudio,

My AD9866 is under 40C during RX, during TX it only raises a degree or two.

I had the same issue on another project that you had with the Ethernet chip.  I had to remove the chip to fix that one.  I never use drag method if there are any unconnected pads!

Stew

KF5KOG

[Steve Haynal]

Great progress Jack!

73,

Steve

KF7O

[Steve Haynal]

Hi Claudio,

I measured my AD9866 with an infrared thermal gun and it reports 45C. It is the hottest IC on the board. But I can keep my finger on it indefinitely without any discomfort. The temperature feels very comparable to how hot the AD9866 runs on the HL1. Just to throw out some ideas you may have already considered, but is the contact between the AD9866 and the PCB uniform and flat? Perhaps reflowing it with hot air will result in a better thermal joining. There also may be some shorted pins drawing excessive current. For example, through reset or mode select, etc. 

Takayashi affixed a nice small heat sink to his AD9866. Maybe we should start recommending that.

Unfortunately the PA transistors are too small for the thermal gun I borrowed to register a good reading. I attempted to determine the spot to distance ratio by measuring the temperature at the tip and various points of my soldering iron, but had trouble with surface areas comparable to the size of the transistors.

73,

Steve

KF7O

[in3otd]

yep, I think I learned now to avoid drag soldering around unconnected pads, hi.
(BTW, I noticed that the KSZ9031RNX datasheet has been updated, seems now a little clearer on the different ground pad sizes for the different part numbers. I got one with the smaller pad, since parts with the larger one were not in stock at Digikey but at least that didn't cause any issue with soldering.)

A cheap infrared thermal gun just over the AD9866 says around 42 °C (in RX) but I'm not sure if it's averaging around an area larger than the IC. I saw that Steve has a thermal connection to the metal enclosure near the PA devices and thought that it could help a bit here also. The overall current drawn from a 12 V supply during RX is around 200 mA here.

73 de Claudio, IN3OTD / DK1CG

[Jack Generaux]

Stew, et. al.,

I am winding T3 and wanted to check on something.  The note says T3 (the output transformer) is  4T primary, 1T+1T secondary 
on BN43-202.   I noticed in your picture it appears that you are using a single wire for the single turn secondary.  I wound a 4 turn secondary (with center tap) and was planning to use two wires in parallel for the single turn secondary, but it appears your having good results with a single wire? Thoughts?   Did you add a resistor on the center tap as Claudio suggested to Steve?  Also did how did you set your bias?  Thank & 73.

Jack (W0FNQ)

[Steve Haynal]

Hi Jack,

I added a resistor for some protection when initially setting the bias. I have removed it now. In the beginning I used a raspberrypi to talk to the potentiometer over i2c but don't recommend that method for you. I am now using the FPGA to talk to the potentiometer. I am working on an enhancement to Quisk which allows selection between low power RF and PA as well as bias setting. I hope to share this sometime this weekend. I would wait for that before attempting to set the bias or use the PA. You could install the latest (4.1.3) Quisk and make sure that is working with low power RF, then there should be no issues with using my enhancements.

73,

Steve

KF7O

[in3otd]

Hello Jack,
I'm not sure I understood how you wound the transformer. The low-impedance side, towards the FETs, must be done with two full turns, with a center tap; a single turn with center tap does not work as expected.
As Steve said, the resistor on the center tap is useful just when experimenting with the bias at the beginning, to make sure to limit the current thru the FETs should something go wrong.

73 de Claudio, IN3OTD / DK1CG

[Jack Generaux]

Thanks Claudio,

I definitely had it wrong.  I have not put in the FETS, so no harm done.  Just starting chasing the IP DHCP issue here.  I may move over to the Linux side -- Windows 10 may not be playing nicely.

73

Jack