Modelsim Se 6.5b Crack 21
Antenor Ketkaew
Now the ModelSim PE Command Reference Manual (modelsim_pe_ref.pdf is behind a Mentor login-wall unfortunately), does not even mention the assertion ... command, the HTML manual (e.g. here) does mention it though.
Lab Overview: Since you are new around here, we need to make sure you have all the tools to be a successful member of the AwesomeCore team. We expect you to have proficiency in both Quartus II and Verilog. In order to get you up to speed, this lab will have you work through a simple tutorial on using Quartus II. If you have worked with this tool in the past, this lab should be very easy. If not, you should get started immediately so you don't fall behind right away. In the future, you will be working with a partner to complete labs but for this lab you should work alone. Good luck!
Lab Deliverables: Since this is an introductory lab, you will not be required to demonstrate anything at the end. The requirements are stated below.
- Demonstration: None
- Progress Report: Answer all the questions that are found in the lab description. There are 9 total questions and they are all located in tables with a light green background. Bring your report to turn in at the beginning of class on Friday, April 9. Late submissions will not be accepted. Also, please staple or bind your report in some way.
Part 1: Install Quartus II and ModelSim: Altera offers a free version of their design suite called Quartus II Web Edition and a free version of ModelSim for Altera. We will be using Quartus II version 9.1 SP2 and ModelSim-Altera Starter Edition version 6.5b, which can be downloaded here.
We encourage you to also work in the CSE labs in the basement of the CSE building. These software tools should be installed on the Windows partitions of all the computers in the lab after the second week of class. Please let us know (via the web forum) if you find lab computers that don't have these tools installed or have an older version of the software. Since the necessary tools will not be installed in the basement labs in time for this first lab, please install the tools on your own machine; the tools are available for Windows and Linux. If you cannot do this, please speak with the professor ASAP.
Part 2: Quartus II Quick Tutorial: Altera provides a nice step-by-step tutorial which will guide you through the basics of creating and working with projects in Quartus II. You only need to work though the first 4 sections. Sections 5 through 8 deal with issues related to FPGA board programming or simulation using Quartus II's built-in simulator (which we will not be using). Also work through the first three chapters of the ModelSim tutorial.
At AwesomeCore, we just bought a couple new Cyclone II FPGAs. To get you started, your manager has given you a Verilog file (adder.v) that describes a basic 8-bit adder. Look at the file and make sure you understand it thoroughly. After doing so, create a new project in Quartus II that contains this adder. When creating the project, set the device to Cyclone II EP2C35F672C6 and simulator to ModelSim-Altera with Verilog HDL.
Note: the Altera tools don't seem to like spaces in filenames and paths, so don't use spaces in any filenames or directory names. This includes the "My Documents" directory; you can create your project on your network drive, which "My Documents" points to anyway--just don't specify the project location using the "My Documents" shortcut. There is a post on the discussion board with a little more detail.
To see what is really going on, perform a behavioral (a.k.a. functional) simulation. Use test_adder.v as your testbench. When you've run the simulation, you should see something like what's in the figure below. Play around ModelSim (and perhaps the testbench) until you feel comfortable with it. You'll be using ModelSim as your primary debugging tool to debug your processor designs this quarter, so get familiar with it.
You might have noticed that output 'isOdd' is updated one cycle later than 'out'. (Stupid...who wrote this?) Anyway, it is a good opportunity to show your ability to tweak a design to get maximum performance. Modify the Verilog file so that 'isOdd' is simultaneously updated with 'out'. Perform the same behavioral simulation you did in the previous step again. (Hint: You may want to examine blocking vs non-blocking assignment in Verilog.) Note: When updating your adder.v, both 'out' and 'isOdd' should be updated the cycle after the input(s) change, not two cycles later.
Now that you have verified that your adder is functionally correct, it is time to synthesize. In the synthesis stage, Quartus translates your Verilog design to what its backend stage (implementation stage) can understand. To synthesize a design, double click on "Analysis and Synthesis" in the Tasks pane. When synthesis is done skim through the generated reports.
Now you'll want to see how your design maps onto the FPGA device. The stage where the design tools find a good layout on the device is called "Place and Route". Run this stage by double clicking on "Fitter" in the Tasks pane. Skim through the generated reports.
Now that the design tools have mapped your design to an FPGA, you can estimate timing and figure out how fast your adder will operate. Now run the whole design compilation chain, which includes a timing analysis: go to "Processing" - "Start Compilation". Look over the reports in the "Classic Timing Analyzer" section. The frequency in the "Clock Setup" section is the maximum clock frequency at which your adder will run. The "tco" is the maximum amount of time from the active clock edge input to the output arriving at an output pin. For more information on timing analysis in Quartus II, see the tutorial on timing.
In order to prove that your adder works at a certain frequency, you need to do a post-route simulation. By comparing the results of your behavior simulation with post-route simulation, you can verify the validity of your implementation. Luckily, you can reuse the testbench from the behavior simulation you did earlier, and the process for running the simulation is very similar. Since the tutorials do not cover how to run timing simulations using ModelSim and a Verilog testbench, here are the instructions you'll need to get started:
- Make sure to run the entire compilation process in Quartus II (including "EDA Netlist Writer").
- Open ModelSim.
- Select "File" - "Change Directory..." and navigate to the "simulation" and then "modelsim" subdirectories under your adder project directory.
- Select "File" - "New" - "Library..." and select "a new library and a logical mapping to it". Name the library "work" and enter "work" for the library physical name as well. You should then see the "work" library at the top of the library list.
- Select the work library and select "Compile" - "Compile...". Select "adder.vo" and then click "Compile". Then navigate to "test_adder.v" (the same testbench file you downloaded before and used for your functional simulation), which should be a couple directories up. Click "Compile" with "test_adder.v" selected. Then click "Done". Now, in the library list, if you expand the "work" library, you should see "adder" and "test_adder". In the future, if you make any changes to adder or testbench Verilog source, you'll need to re-compile the "work" library before re-simulating.
- Select "Simulate" - "Start Simulation".
- In the "Design" tab, expand the "work" library and highlight "test_adder". Select "ns" in the "Resolution" drop-down field.
- In the "Libraries" tab, in the "Search Libraries" area, select "Add" and add the "cycloneii_ver" library.
- In the "SDF" tab, select "Add". Add "adder_v.sdo" and apply it to the region "/test_adder/dut".
- Finally, click on "OK" to start the simulation. After this, use ModelSim to run the timing simulation in the same manner you used it to run the functional simulation.
Part 4: 32-bit Adder Now that you have a working, validated 8-bit adder, you should turn your attention towards bigger and better designs. One simple extension you can do is to modify your adder to support 32-bit addition rather than just 8-bit. Modify your Verilog source file then synthesize and implement it.
Generally, the bigger and more complex your design is, the slower it will be. It is important to understand the main causes of this phenomenon:
- Bigger/more complex logic usually requires more logic cells for implementation. This will often lead to an increase in logic delays.
- Increasing the number of logic cells also increases the difficulty of finding the optimal placement and routing for the circuit. As a result, you end up with a suboptimal circuit which is slower than it could be.
Part 5: Register File Now that you are a master of adders, it is time to move on to bigger and better things. Your next task is to design a register file. Go ahead and create a new project for your register file design. Processors keep a small, but extremely fast collection of storage locations, called registers, grouped into what is called a register file. You'll design a register file with 2 read ports and 1 write port, so that every cycle two registers can be read and one written. You should parametrize your register file with number of registers and data width (the number of bits in each register). You can set the default parameters to 6 16-bit registers. Your register file should take as input:
- a clock signal (call it clock)
- a write_enable signal (asserted when a value is to be written to a registers)
- a write register number (call it write_reg) to specify which register to write
- a value to write to the given register (call it data_in)
- and two register numbers to select which registers to read (call them read_reg0 and read_reg1).