GSOC-2018 : Create a "Integrated Bit Error Ratio Tester" (iBERT) - Akhil Singh

[Akhil Singh]

Hi,

This time I am selected for GSOC-2018 in Timvideos for the project 'Create a "Integrated Bit Error Ratio Tester" (iBERT)'.

The aim of this project is to create a litescope based "Integrated Bit Error Ratio Tester" (iBERT) clone. This project has three parts:

a) Data sequence generators + checkers. These generate given bit data stream, then after transmission and receiving check that the bit data stream is correct. 

b) Data channel wrappers. These give you a common interface to controlling the parameters of a channel used in transmission and receiving. For simple data channels this might just provide clock control. For more advanced channels, like the high speed transceivers, this provides things like controlling parameters like pre-emphasis, equalisation, etc.

 

c) Host computer Control GUI / Console. This gives a nice interface for controlling all the parameters and seeing the results of various tests.

URL of the
      1.  project proposal

      2.  Blog

      3. Github username : akhil-123

Talking about myself

I am Akhil Singh, a third year B.Tech student from the International Institute of Information Technology, Hyderabad. My major interests are in VLSI designing, Embedded Hardware Designing, Digital logic circuits and Image Processing, machine learning. Apart from academics I am a state level player of Table tennis and love to play and watch cricket.  

Contact details:

Mb. number ; +91-8004948595

Email address :  1997sin...@gmail.com

                           akhil...@research.iiit.ac.in