GSoC 2016 : Adding USB 3.0 Support

[Shashank Gangrade]

Greetings!

I am Shashank Gangrade, fourth year undergraduate student at Indian Institute of Technology, Mumbai. I am doing an integrated dual degree course with Bachelors in Electrical Engineering and Masters in Microelectronics and VLSI. I have been interested in VLSI Design and Embedded Systems, and would like to apply for GSoC under HDMI2USB project of TimVideos.

I am familiar with HDLs (Verilog and VHDL) and PCB Design Suite(Eagle).

I am interested in the project regarding adding USB 3.0 support to HDMI2USB-misoc-firmware.(link)

I have reading about the USB 3.0 support issue on github. As proposed Daisho USB 3.0 core can be used for this purpose. As Daisho was developed for Altera Cyclone V and the FPGA currently being used is Spartan-6, porting to a different FPGA will be the initial task. Also the Daisho USB 3.0 core uses TUSB1310A transceiver IC, whereas we can use inbuilt high speed transceiver in Spartan-6. Further work will be development of ULPI compatible core initially and then further development of PIPE compatible core for using the high speed transceivers. I am not sure how the two protocols(ULPI and PIPE) are different? Is related to 2.0 and 3.0? Or is it something related to different protocol at different abstraction layer? I believe this is the core part of project and understanding this should be important.
I have also gone through this page which discussed a lot of things about this project.

Also the USB 3.0 support will be through a TOFE expansion board. I have some experience with Eagle for PCB design, but I can also start exploring KiCad for the same. I am currently exploring the possibility of issuing an high speed FPGA from the HPC Lab of my department so that I can do some initial work on that.

Can the prospective mentors please guide me regarding how to proceed with furthers tasks for GSoC application. I was thinking of implementing basic hardware with misoc-firmware, which I am not familiar with right now.

Thanks and Regards

Shashank Gangrade
Senior Undergraduate

Electrical Engineering

IIT Bombay

[Tim Ansell]

Hi Shashank,

On 4 March 2016 at 01:39, Shashank Gangrade <shashank...@gmail.com> wrote:

Greetings!

I am Shashank Gangrade, fourth year undergraduate student at Indian Institute of Technology, Mumbai. I am doing an integrated dual degree course with Bachelors in Electrical Engineering and Masters in Microelectronics and VLSI. I have been interested in VLSI Design and Embedded Systems, and would like to apply for GSoC under HDMI2USB project of TimVideos. 

 

I am familiar with HDLs (Verilog and VHDL) and PCB Design Suite(Eagle).

I am interested in the project regarding adding USB 3.0 support to HDMI2USB-misoc-firmware.(link)

Thanks for the detailed information, we are very interested in having someone work on the USB3.0 related stuff.

 

I have reading about the USB 3.0 support issue on github. As proposed Daisho USB 3.0 core can be used for this purpose. As Daisho was developed for Altera Cyclone V and the FPGA currently being used is Spartan-6, porting to a different FPGA will be the initial task. Also the Daisho USB 3.0 core uses TUSB1310A transceiver IC, whereas we can use inbuilt high speed transceiver in Spartan-6. Further work will be development of ULPI compatible core initially and then further development of PIPE compatible core for using the high speed transceivers.

 

The work required to do all of;

 * Porting the Daisho core to the Spartan 6 FPGA

 * Adding support for using high speed transceivers (instead of external TUSB1310A transceiver IC)

 * Creating a TOFE expansion board with a TUSB1310A

Is significantly larger than what can be achieved in 3 months.

It is recommended that you choose to either;

 1) Port the Daisho core to the Spartan 6 FPGA + Create a TOFE expansion board with TUSB1310A

/or/

 2) Add support for using high speed transceivers on the Daisho core (with Altera based FPGAs).

I am not sure how the two protocols(ULPI and PIPE) are different? Is related to 2.0 and 3.0? Or is it something related to different protocol at different abstraction layer? I believe this is the core part of project and understanding this should be important.

As USB3.0 is backwards compatible with USB2.0, any USB3.0 core must also implement a USB2.0 core.

ULPI and UTMI are the standards for a USB2.0 transceiver.

PIPE is the standard for USB3.0 (and PCI-Express) transceiver.

 

I have also gone through this page which discussed a lot of things about this project.

This proposal mainly covers the second project above (the high speed transceivers).

 

Also the USB 3.0 support will be through a TOFE expansion board. I have some experience with Eagle for PCB design, but I can also start exploring KiCad for the same.

The TOFE expansion board should have the TUSB1310A transceiver on it. 

The first important step is to figure out if there are enough pins on the Opsis's TOFE connector to make this possible.

I believe a previous student showed that it wasn't possible to use a TUSB1310A with the Digilent Atlys's VHDCI connector because it didn't have enough pins. (See https://logs.timvideos.us/%23timvideos/%23timvideos.2014-04-12.log.html#t2014-04-12T06:49:12 and https://docs.google.com/document/d/1mSsx7gjOm4nj460IL3m9hA8MSBMWLZSOHiKCEbIEVfs/edit# )

We would want any hardware designed to be created in KiCad. We also have templates for creating TOFE boards at https://github.com/timvideos/HDMI2USB-TOFE-kicad-template

I am currently exploring the possibility of issuing an high speed FPGA from the HPC Lab of my department so that I can do some initial work on that.

Getting access to high speed FPGA hardware is a definite requirement for doing the second project. If you need someone from the TimVideos project to explain to the HPC Lab what is going on, I'm happy to chat with them.

For the first project you could purchase a Numato Opsis board, I'm looking at getting a discount (or possibly free) board for accepted GSoC students.

In all cases, you are likely to want access to a very high speed oscilloscope.

Can the prospective mentors please guide me regarding how to proceed with furthers tasks for GSoC application. I was thinking of implementing basic hardware with misoc-firmware, which I am not familiar with right now.

For this project, you are most likely to work independently of the misoc firmware. Once the Daisho core is working on the Spartan 6, we would then look at wrapping it for use inside the misoc firmware.

It is still recommended that you get the misoc firmware up and running by following the instructions at https://github.com/timvideos/HDMI2USB-misoc-firmware/tree/master/scripts

Hope that helps,

Tim 'mithro' Ansell

[Shashank Gangrade]

Hi Tim,

Thanks for your detailed reply.

I would like to focus on the first project
Port the Daisho core to the Spartan 6 FPGA + Create a TOFE expansion board with TUSB1310A. I assume the final goal of this project would be working USB 3.0 port for the Numato Opsis Board. 

Regarding validation of pin count for Opsis's TOFE connecter. After a lot of research on USB 3.0 and 2.0 protocols and how it communicates with TUSB1310A, I found this little spreadsheet, which had all the relevant work done before hand.

Available on TOFE:
LVDS Pair (upto 34) + Clock Pairs (upto 7) + Low speed IO (11)
Total IO Pins: 79

Required:

59(PIPE) + 12(ULPI) + 4(JTAG) = 75

Total 75 I/O Connections and 3 clock. So the USB 3.0 connection should be alright, which I guessed you guys would have kept in mind during the design iterations of Opsis board.

I have also started to play around with the KiCad for PCB designing part of the project. In a few days I can submit patch for the current open issues, when I get more acquainted with the software. I am also looking to get the misoc framework up and running on my system. I am asking around for hardware requirements (FPGA and High speed oscilloscope) in my department.

I have also started looking into the Daisho's USB3.0 Core, which will be the fundamental non-trivial part fo the project. The core is written for Altera Cyclone IV, using the Altera Quartus II build system. The controller uses a lot of Quartus specific features like PLLs, pipelined DDR I/O, distributed block RAM. So porting to Spartan would require using the Xilinx equivalent tools for the same results. I will read more about the core and USB implementation in coming days and will keep you informed regarding the same.

Although I am looking into these things, what initial qualification tasks would you propose I should do for my GSoC application. 

Thanks and Regards

-Shashank Gangrade

[Tim Ansell]

On 9 March 2016 at 02:09, Shashank Gangrade <shashank...@gmail.com> wrote:

Hi Tim,

Thanks for your detailed reply.

I would like to focus on the first project
Port the Daisho core to the Spartan 6 FPGA + Create a TOFE expansion board with TUSB1310A. I assume the final goal of this project would be working USB 3.0 port for the Numato Opsis Board. 

Correct, a "working" USB 3.0 port on the Numato Opsis board would be the end goal. It would be awesome if you had working video capture via the USB 3.0 port but just demonstrating that the USB 3.0 interface is correctly identified by a computer and able to stream at multi-gigabit speeds would be enough for GSoC.

 

Regarding validation of pin count for Opsis's TOFE connecter. After a lot of research on USB 3.0 and 2.0 protocols and how it communicates with TUSB1310A, I found this little spreadsheet, which had all the relevant work done before hand.

I created that spreadsheet :)

 

Available on TOFE:
LVDS Pair (upto 34) + Clock Pairs (upto 7) + Low speed IO (11)
Total IO Pins: 79

Please note that like PCI Express, TOFE has different size connectors -- 1x, 4x, 8x and 16x. Als,o like PCI Express, large connectors are compatible with smaller versions (IE an 4x board can be used in a 8x/16x connector).

 

Required:

59(PIPE) + 12(ULPI) + 4(JTAG) = 75

Total 75 I/O Connections and 3 clock. So the USB 3.0 connection should be alright, which I guessed you guys would have kept in mind during the design iterations of Opsis board.

The Opsis board only has a 8x TOFE connector, not a 16x TOFE connector.

This means you only get;

DIFF IO*	34
DIFF GCLK*	10
IO*	1
Total IO Pins	45

I think you will need to do further analysis to see if there is a way to solve this problem. Questions to look into;

 * Are all the IO pins actually needed on the PIPE interface in our use case?

 * Are some pins suitable for being connected to something like an I2C IO expander? (Such as being configuration or very low speed changing.)

 

I have also started to play around with the KiCad for PCB designing part of the project.

I recommend joining the #hackvana, #kicad and #timvideos channels on freenode to get help with using KiCad.

 

In a few days I can submit patch for the current open issues, when I get more acquainted with the software.

If you need help getting started with the software, please try the #timvideos and #daisho channels on freenode. The #daisho channel might take a couple of hours to respond (maybe as much as 24 hours), so please be patient.

I am also looking to get the misoc framework up and running on my system. I am asking around for hardware requirements (FPGA and High speed oscilloscope) in my department.

Great!

 

I have also started looking into the Daisho's USB3.0 Core, which will be the fundamental non-trivial part fo the project. The core is written for Altera Cyclone IV, using the Altera Quartus II build system.

Correct. One of the first steps would probably be to see if you could replicate their work. That would require getting hold of 

 

The controller uses a lot of Quartus specific features like PLLs, pipelined DDR I/O, distributed block RAM. So porting to Spartan would require using the Xilinx equivalent tools for the same results. I will read more about the core and USB implementation in coming days and will keep you informed regarding the same.

There is a document which includes information on porting the Daisho core. This will require figuring out what exactly they used for that.

 

Although I am looking into these things, what initial qualification tasks would you propose I should do for my GSoC application. 

I recommend starting a Google Doc and start documenting information about what you are going to try and achieve and how you are going to achieve that. You can flesh it out as you add more details and figure out how things would work.

Here are a couple of examples of previously accepted students applications along similar lines;

 * Ajit's MJPEG Optimisation Proposal - https://docs.google.com/document/d/1akF6lBb78OWTGFosnYUC5-MxuNZXCrCob70ga3uQB8A/edit

 * Rohit's VGA Expansion Board Proposal - https://docs.google.com/document/d/1GJPIXspg5hRtFHwYyNCyEvysvAO9L9YQFxz_E6E2Sno/edit#

Tim 'mithro' Ansell

[Shashank Gangrade]

Hi Tim,

Apologies for the late reply. I also tried to connecting with you on IRC but couldn't so I am posting my detailed findings and questions here.

So I had somehow assumed that Opsis had 16x TOFE connector. But with 8x connector, there are total 45 I/O between the expansion board and  Opsis board.
For USB 3.0, PIPE interface will have 16bit RX and TX along with clock which makes a total of 34 high speed pins @250MHz, rest of them are control/status bits.
For USB 2.0, ULPI interface will have 8bit data + clock@60MHz, 9 pins rest are control bits. 
Referred from datasheet of TUSB1310A IC. 

Availability is 45 I/O pins, which includes 34 LVDS (DIFF I/O) +10 GCLK + 1 I/O.

I had a few ideas regarding this,
1. Can we use a MUX kind of logic to share pins between PIPE and ULPI interface. This is because at any point of time only one of them will be used.
2. Can the 34 DIFF I/O pins be configured such that each pin is independent I/O, that will then directly give 68 pins.
3. Assuming the above two don't work, then excluding the requirements for high speed PIPE interface(34) + ULPI interface(9) , only 2 pins will be left for rest all of the control signals and other overhead connections. This will be very close call and will require more research regarding I2C expanders.

If the pin count is not sufficient, then we might need to look into using the high speed transceivers in Spartan-6 instead of using transceiver IC. But this will be a more difficult task because daisho core is developed to using with transceiver IC, and will require a lot more development. 

I was also asking around for high speed oscilloscope, and the maximum available was around 5GHz bandwidth. I read somewhere the recommended specifications are upto 10GHz. So will this be a problem for final testing and working of the boards. Is there a cheap alternative to using high speed oscilloscopes.

I had already created the doc you had mentioned. I will also share my first proposal draft by Saturday to get it reviewed. But, before this pin count validity needs to be verified. Also if possible we can discuss these ideas on IRC by fixing a common time.

-Shashank Gangrade

[Tim Ansell]

On 17 March 2016 at 10:23, Shashank Gangrade <shashank...@gmail.com> wrote:

Hi Tim,

Apologies for the late reply. I also tried to connecting with you on IRC but couldn't so I am posting my detailed findings and questions here.

So I had somehow assumed that Opsis had 16x TOFE connector. But with 8x connector, there are total 45 I/O between the expansion board and  Opsis board.
For USB 3.0, PIPE interface will have 16bit RX and TX along with clock which makes a total of 34 high speed pins @250MHz, rest of them are control/status bits.

So here you need 34 pins or 34 diff pairs?

 

For USB 2.0, ULPI interface will have 8bit data + clock@60MHz, 9 pins rest are control bits. 
Referred from datasheet of TUSB1310A IC. 

Availability is 45 I/O pins, which includes 34 LVDS (DIFF I/O) +10 GCLK + 1 I/O.

The GCLK pins can be used as I/O pins. They are just connected to the "global clock network" (hence GCLK in the FPGA).

There are only 45 I/O pins available. They can be configured as 22 differential pairs (and 1 singled ended IO) or 45 singled ended IO.

 

I had a few ideas regarding this,
1. Can we use a MUX kind of logic to share pins between PIPE and ULPI interface. This is because at any point of time only one of them will be used.

This is an option, but as it makes things more complex we should try and avoid it as much as possible.

 

2. Can the 34 DIFF I/O pins be configured such that each pin is independent I/O, that will then directly give 68 pins.

The IO pins can be configured in any standard supported by the Xilinx Spartan-6 FPGA when the IO bank is supplied with a VCCIO of 3V3 and a VAUX of 3V3. This includes both differential and single ended standards.

See http://www.xilinx.com/support/documentation/user_guides/ug381.pdf for more information.

 

3. Assuming the above two don't work, then excluding the requirements for high speed PIPE interface(34) + ULPI interface(9) , only 2 pins will be left for rest all of the control signals and other overhead connections. This will be very close call and will require more research regarding I2C expanders.

An I2C expanded can be connected to the I2C configuration bus (SMCLK/SMDAT) without using any extra pins.

 

If the pin count is not sufficient, then we might need to look into using the high speed transceivers in Spartan-6 instead of using transceiver IC. But this will be a more difficult task because daisho core is developed to using with transceiver IC, and will require a lot more development. 

Having a working high speed oscilloscope will be a must here. Also note that the high speed transceivers on the Opsis are not fast enough to be used for USB3.0 (they each operate at 3Gbit/s and USB3.0 needs 5Gbit/s).

 

I was also asking around for high speed oscilloscope, and the maximum available was around 5GHz bandwidth. I read somewhere the recommended specifications are upto 10GHz. So will this be a problem for final testing and working of the boards. Is there a cheap alternative to using high speed oscilloscopes.

You are more interested in what the sample rate of the oscilloscope is. You want a sample rate which is at least 4 times the rate of the signal you want to look at.

I had already created the doc you had mentioned. I will also share my first proposal draft by Saturday to get it reviewed.

Please share the document even if it has yet to be completed. 

 

But, before this pin count validity needs to be verified. Also if possible we can discuss these ideas on IRC by fixing a common time.

I'm generally around from 1pm till about 8pm in Sydney/Australia time zone.

Tim 'mithro' Ansell