GSOC-2017 : Conversion of JPEG encoder from VHDL to Migen/Misoc - Ishan_Bansal

[Ishan Bansal]

Hi,

This time I am selected for GSOC-2017 in Timvedios for the project 'Conversion of JPEG encoder from VHDL to Migen/Misoc' under the HDMI2USB-litex-firmware repository.

The aim of the project is to implement different modules of JPEG encoder in migen (python library) from the previously written VHDL code along with the test benches in order to check the performance of the JPEG encoder.

URL of the
      1.  project proposal

      2.  progress report (blog)

      3. Github username : ishan98

Talking about myself

I am Ishan Bansal, a second year B.Tech student from the International Institute of Information Technology, Hyderabad. My major interests are in VLSI designing, Embedded Hardware Designing, Digital logic circuits and Image Processing. Apart from academics I like to do sketching and playing football ( doesn't mean I am good at that ) and most importantly love to watch a lot of cartoons. 

Contact details:

Mb. number ; 91-9815196239

Email address :  bansal...@gmail.com

                         ishan....@students.iiit.ac.in

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