TAPR-HamSCI Technical Session Tonight

[Dr. Nathaniel A. Frissell Ph.D.]

Hi everyone,

 

The TAPR-HamSCI Technical Session will take place tonight starting at 9 PM Eastern Daylight Time (0100z).

Here is the zoom link : https://scranton.zoom.us/j/91432247420?pwd=VWE5NnFhcUZIc04wWjkvcCtkbWJ4UT09

 

See you tonight!

 

73 Nathaniel W2NAF

 

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Topic: TAPR-HamSCI Technical Session

 

Time: This is a recurring meeting Meet anytime

 

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--------------------------------------------------

Nathaniel A. Frissell, Ph.D., W2NAF
nathaniel...@scranton.edu
Associate Professor
Department of Physics and Engineering
University of Scranton
HamSCI Lead

 

 

[David Hostetler]

I have been reviewing the HamSci 2024 Receiver Requirements document rev 0.3 and have a few notes.

pg 6: there is a typo in the first line of the table: "+/-50 nsec intra-system" should be "inter-system"

In Section 2 Power Supply: rather than attempting to specify the internal operating voltages and currents, we should specify the external power inputs. For example, say: 

2. Input Power, I

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[David Hostetler]

Apologies for the repeat message, hit the wrong key and sent  before done.

I have been reviewing the HamSci 2024 Receiver Requirements document rev 0.3 and have a few notes.

pg 6: there is a typo in the first line of the table: "+/-50 nsec intra-system" should be "inter-system"

In Section 2 Power Supply: rather than attempting to specify the internal operating voltages and currents, we should specify the external power inputs. For example, say: 

"2. Input Power

If at all possible the unit should be powered from the USB connection; if more power is required a standard 12 VDC connector will be utilized."

pg 7: typo: GB/s should be Gb/s

pg 7: ADC overload: is this a visual indicator on the device and/or an electrical signal to the host computer?

3.2 Clock Interfaces: for at least the Grade 1 clock performance and single channel receiver, I think it would be good to have a built-in GPSDO.

3.3 Antenna Interface: should we add the ability to power a preamp from the SMA input?

4.5 Noise Source: Do we need a tolerance on the noise level provided? Will this be a factory calibration? Is this noise source just to perform a rough test that the front end hasn't been blown up? Will only one output level be enough to verify any attenuators that are built-in and switchable?

Clock jitter: There are many types of jitter measurement. In the LTC2208 spec I see this specifically as RMS jitter, but in our document I see on pg 8 two places where jitter is mentioned "1+ psec jitter" and "1 psec jitter" without being specific and on pg 10, I see "+/-1 psec jitter, peak". 

On pg 10, there is a graph at the top. It seems like this is being referenced in the NOTE in section 4.3 Clock Jitter and from the text in the NOTE the graph should be below the note. I am also wondering about the 0 fs line and if it is properly labeled.

Section 4.4 Clock Phase Noise: One of the bullet points: "The phase noise is specified at 30 MHz" If we don't have a 30 MHz clock in the new design, I am not sure what to do with this.

I am still working through understanding the clock performance requirements and how they relate to the final receiver performance. I am also interested in how the clock jitter and phase noise will be confirmed during the prototype stage.

Dave, W6OQ