Post-synthesis gate-level simulation with ASAP7 SRAMS

[Li Yang Kat]

Hello all,

I've been trying to do post-synthesis simulation for a Rocket core design with the Gemmini systolic array RoCC accelerator using ASAP7 technology and the provided test harness. I've tried doing this through the hammer flow and also running the simulation command to compile the simv binary manually. Unfortunately, neither of these methods are working. In my most recent attempt, the AXI master on the Rocket core keeps issuing reads but no data is returned.

Here is the command I used to generate the simv binary: 

rm -rf csrc && vcs -full64 -notice -line -CC "-I/share/instsww/synopsys-new/vcs/P-2019.06/include" -CC "-I/home/ff/ee290-2/ee290-2-esp-tools/include" -CC "-I/scratch/ee290-2-abb/test1/tools/DRAMSim2" -CC "-std=c++11" /scratch/ee290-2-abb/test1/tools/DRAMSim2/libdramsim.a /home/ff/ee290-2/ee290-2-esp-tools/lib/libfesvr.a +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet -q +rad +v2k +vcs+lic+wait +vc+list -error=noZMMCM -assert svaext -sverilog +vcs+initreg+random +libext+.v +incdir+/scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/ -f /scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/sim_files.common.f /scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/chipyard.TestHarness.GemminiRocketConfig.harness.v /scratch/ee290-2-abb/test1/vlsi/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/syn-rundir/Top.mapped.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_SRAM_TT.v +define+VCS +define+CLOCK_PERIOD=1.0 +define+PRINTF_COND=TestDriver.printf_cond +define+STOP_COND=\!TestDriver.reset +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN -o simv +define+DEBUG -debug_pp

And here's the command I used to run the simulation:

./simv +permissive +vcs+initreg+0 +vcs+initmem+0 +max-cycles=100000 +verbose +vcdplusfile=vcdplus.vpd +permissive-off ../../../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/template-baremetal

I'm not entirely sure what's wrong but I suspect it has to do with the register and memory initialization. I have used the VCS options to set all of them to zero but it doesn't seem to work. I was hoping someone could advise me on what I need to take note of during post-synthesis gate-level simulation and how I could go about trying to debug this.

Thank you!

[Li Yang Kat]

I'm sorry I realized the image is really small. Here's a link to the original: https://drive.google.com/file/d/1mGO-fI2kv9P-8-7uKEsCbtX6bxWUmZ3W/view?usp=sharing

[Colin Schmidt]

Hello and thanks for your question,

I would recommend against running the commands manually. Its fine to inspect them but its easy to make mistakes that way and you will have less reproducible results.

I have 2 suggestions depending on your situation.

If you aren't using a timing annotated simulation:

Are you setting `sim.inputs.level: gl`? 
If you do that hammer should initialize all the sequential cells.

If you haven't set this you would be likely to see Xs appear in the simulation eventually.

If you are using a timing annotated simulation:

The default chipyard designs do not synchronize the AXI interface with the incoming clock. This means that depending on the input and output constraints you gave the synthesis tools you likely have timing violations on that interface.

You should consider adjusting your input and output delays via the hammer key `vlsi.inputs.delays`

Thanks,

Colin

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[Li Yang Kat]

Hi Colin,

Thanks for the tips. I've actually tried doing the simulation through the hammer flow, that is doing the syn-to-sim and subsequently sim processes. The force_regs.ucli file appeared to force all registers to zero. However, X's still subsequently appeared when I did that, which I suspected was because of the ASAP7 behavioral SRAM model both not being initialized and outputting high Z's when the SRAMS are read/write disabled. I modified the behavioral SRAM to remove these features in an attempt to avoid the associated problems. This still caused X's until I manually ran the commands above. 

Yes, I have set sim.inputs.level: 'gl' and have disabled timing annotated simulation. 

Is there any sample .yml configuration file I could refer to for post-synthesis simulation? I think I am missing something small but I'm not sure where.

Thank you!

On Wednesday, 22 April 2020 10:22:03 UTC-7, colins wrote:

Hello and thanks for your question,

I would recommend against running the commands manually. Its fine to inspect them but its easy to make mistakes that way and you will have less reproducible results.

I have 2 suggestions depending on your situation.

If you aren't using a timing annotated simulation:

Are you setting `sim.inputs.level: gl`? 
If you do that hammer should initialize all the sequential cells.

If you haven't set this you would be likely to see Xs appear in the simulation eventually.

If you are using a timing annotated simulation:

The default chipyard designs do not synchronize the AXI interface with the incoming clock. This means that depending on the input and output constraints you gave the synthesis tools you likely have timing violations on that interface.

You should consider adjusting your input and output delays via the hammer key `vlsi.inputs.delays`

Thanks,

Colin

On Mon, Apr 20, 2020 at 2:23 PM Li Yang Kat <kat....@gmail.com> wrote:

I'm sorry I realized the image is really small. Here's a link to the original: https://drive.google.com/file/d/1mGO-fI2kv9P-8-7uKEsCbtX6bxWUmZ3W/view?usp=sharing

On Monday, 20 April 2020 14:21:12 UTC-7, Li Yang Kat wrote:

Hello all,

I've been trying to do post-synthesis simulation for a Rocket core design with the Gemmini systolic array RoCC accelerator using ASAP7 technology and the provided test harness. I've tried doing this through the hammer flow and also running the simulation command to compile the simv binary manually. Unfortunately, neither of these methods are working. In my most recent attempt, the AXI master on the Rocket core keeps issuing reads but no data is returned.

Here is the command I used to generate the simv binary: 

rm -rf csrc && vcs -full64 -notice -line -CC "-I/share/instsww/synopsys-new/vcs/P-2019.06/include" -CC "-I/home/ff/ee290-2/ee290-2-esp-tools/include" -CC "-I/scratch/ee290-2-abb/test1/tools/DRAMSim2" -CC "-std=c++11" /scratch/ee290-2-abb/test1/tools/DRAMSim2/libdramsim.a /home/ff/ee290-2/ee290-2-esp-tools/lib/libfesvr.a +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet -q +rad +v2k +vcs+lic+wait +vc+list -error=noZMMCM -assert svaext -sverilog +vcs+initreg+random +libext+.v +incdir+/scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/ -f /scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/sim_files.common.f /scratch/ee290-2-abb/test1/vlsi/generated-src/chipyard.TestHarness.GemminiRocketConfig/chipyard.TestHarness.GemminiRocketConfig.harness.v /scratch/ee290-2-abb/test1/vlsi/hammer/src/hammer-vlsi/technology/asap7/sram_compiler/memories/behavioral/sram_behav_models.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/syn-rundir/Top.mapped.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SIMPLE_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_AO_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_OA_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_SEQ_SRAM_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_RVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_LVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_SLVT_TT.v /scratch/ee290-2-abb/test1/vlsi/build/chipyard.TestHarness.GemminiRocketConfig-Top/tech-asap7-cache/extracted/ASAP7_PDKandLIB.tar/ASAP7_PDKandLIB_v1p5/asap7libs_24.tar.bz2/asap7libs_24/verilog/asap7sc7p5t_24_INVBUF_SRAM_TT.v +define+VCS +define+CLOCK_PERIOD=1.0 +define+PRINTF_COND=TestDriver.printf_cond +define+STOP_COND=\!TestDriver.reset +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN -o simv +define+DEBUG -debug_pp

And here's the command I used to run the simulation:

./simv +permissive +vcs+initreg+0 +vcs+initmem+0 +max-cycles=100000 +verbose +vcdplusfile=vcdplus.vpd +permissive-off ../../../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/template-baremetal

I'm not entirely sure what's wrong but I suspect it has to do with the register and memory initialization. I have used the VCS options to set all of them to zero but it doesn't seem to work. I was hoping someone could advise me on what I need to take note of during post-synthesis gate-level simulation and how I could go about trying to debug this.

Thank you!

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