This is an area that I have been wondering about.
After updating the tables, there is an invalidation of the TLB. That includes a data barrier to ensure the CPU has completed the writes to the table and the barrier is `__asm__ volatile` to ensure the compiler doesn't move things after the barrier. The point of invalidation is the point at which we say that the tables are in their final state so it doesn't seem to matter exactly the order that writes happen within the existing constraints?
I've also wondered about the need for cache maintenance. We currently don't flush the tables or mark them as uncached memory but we haven't run into any issues with it yet. That would suggest the MMU is also using the cache however I haven't confirmed this yet in the documentation so any pointers on that would be appreciated.
Thanks
Andrew