Xilinx Nexys A7

[Daria]

Atthis point in time, I would recommend reinstalling the Digilent Cable drivers; Xilinx has an answer record on how to do that here: I know you have tried a couple of USB cables already, but if the cable drivers do not help, I would also recommend trying another USB port and potentially another cable that is known to transfer data; the only reason I recommend this is because this has happened to other users of the Nexys 4 DDR boards in the past.

Also what OS are you using? If you are using Linux then you need to manually install the Digilent Cable Drivers. If windows, are you able to see the Nexys 4 DDR in the device manager under ports and Universal serial bus controllers? Please download Adept 2 here. Are you able to see the nexys 4 in Adept 2?

As for Vivado, ML Standard Edition will work with the Nexys Video, however, you should be aware that the example projects Digilent provides may or may not be supported. The most up-to-date (but still marked under construction as they haven't been fully tested) materials, supporting Vivado 2020.1, can be found here: -logic/nexys-video/demos/start

How exactly, are readers expected to interpret this sentence ? Most people would probably assume that they can just download the archived project files and generate a bitstream file that works as advertised with minimal effort. They would assume that any Xilinx IP used would be free to use without an evaluation license.

I've used the latest ML edition of the tools on both Win10 Pro and Ubuntu 20.04 but since installing it have found that it takes a very long time to bring up any of the Vivado editions that are installed, sometimes resulting in a timeout error ( though it does eventually start anyway ).

I believe that the edition of the tools that users probably want to use depends on a lot of factors, like device support ( ML supports the most ) and what they want to do, and what design flow they prefer. Xilinx IP might be free in one version and not in another. Vitis 2021.2 is a 60+ GB install and Vivado 2017.3 plus the SDK is about 10% of that. Either can support anything that the Nexys Video board is capable of. As you point out it is usually possible to install the Xilinx tools on host OS versions not specifically supported by Xilinx; though sometimes this involves some unexpected work-arounds.

That was pretty vague on my part, apologies. I should have said that XPR and workspace files which can be opened in Vivado and Vitis 2020.1 exist, however, I haven't personally had the opportunity to check whether their documentation is accurate to the steps needed to get them running. The documentation may be incomplete and the projects may be buggy. I'm looking into it.

It looks like you downloaded the "Source Files" zip on Github which does not contain sources as you noted. The correct downloads should be the -hw.xpr.zip and -sw.ide.zip files, as pointed out in the release description. I'll be updating these reference pages to make sure that they point directly to the file downloads, as opposed to the GitHub page, as the use of the releases page has definitely been confusing.

The IP in this download were packaged with Vivado 2016.4, and are locked until you upgrade them - Vivado ships with only the most recent version of any particular IP core used. Upgrade the IP by navigating through Reports -> Report IP Status -> Upgrade Selected, as below. Since the affected IP only increment the minor version, no port name changes (that would require modifications to verilog sources) should be present. I've verified that (despite the language server freezing and requiring me to kill and restart the 2022.1 instance) a bitstream can be generated after doing this.

FPGAs seem like lots of fun but the initial investment in time and energy to get up and running with one is so very high. I recently had a little bit of time (and motivation) to learn a little about how to get up and running with Vivado and VHDL on an FPGA (I have some previous experience from some years ago with Vivado and HLS, this is slightly similar). When having gone through some kind of hurdle, I feel it is nice to try to make it a bit easier for the next person by writing about the experience.

The FPGA used here is the Artix 7 on a Nexys A7-100t board from Digilent. I know there are probably already lots of "how-to" manuals for this but this one will be from my perspective as somewhat of an FPGA noob! I hope that leads to a somewhat different point of view.

The authors will not be liable for any errors or omissions in this information nor for the availability of this information. The authors will not be liable for any losses, injuries, or damages from the display or use of this information.

There is a little bit of setup needed to get started. This comes in the form of "board files" containing parameters for a particular type of FPGA development board. Digilent provides board files in a github repository.

Locate the directory where you installed Vivado and check for this subdirectory //data/boards/board_files. If you already have a nexys-a7-100t sub folder located there, you do not need to do anything. But if not you should grab the board files from Digilent github, unzip the archive and locate nexys-a7-100t directory. This directory will be under a subdirectory called new/board_files.

Task: Click on Create Project. You find this in the Quick Start area. This starts up the Create a New Vivado Project wizard. the first thing it does is show a little wizard welcome screen. Just click next here.

Task: Make up a name for the project and pick a location for the project related files. Check the Create project subdirectory checkbox. Click next to move on to the next setting. I called my project "Blinky" as that is where I hope this will be going.

The next step is to select the FPGA board to use as target. Locate the two tabs Parts and Boards and switch to tab Boards. You can narrow the list of selections down a bit by typing "nexys a7" into the search field.

The GUI is divided into two main areas, a left Flow Navigator and a right side that changes quite a bit depending on what is currently going on. Right now the right hand side of the GUI is showing the Project Manager

TASK: In the Project Manager locate the Sources pane and right click within it. This brings up a list of choices, click on Add Sources. We are going to add a design source so check the Add or create design sources option and click next.

Task: Click on the Create File button and provide a name for the file. I call mine blinky click ok in the Create File dialog and then click Finish in the Add Sources window. After clicking Finish a Define Module dialog appears. This dialog lets you specify interface for the module if you wish, but I am going to do that by typing the VHDL manually. So just click Ok in this dialog.

For the architecture (implementation of the entity) with my limited experience, I have a feeling it would work with a state machine that either is in a Led is on or Led is off state and that it remains in these states for some number of clock ticks. So, we need a way to maintain state and a way to count ticks. For the counter I will use an unsigned, so using IEEE.NUMERIC_STD will be needed.

So, now there are two states LED_On and LED_Off the s signal can be set to one of these states and a counter that can count all the way up to some high number above 33 million. Don't know yet for how long the LED must be in on and off state (number of ticks) for it to visibly blink.

What we want to implement now is hardware that sets the led signal to one when in the On State and zero when in Off, we also want to increment a counter each clock tick and check if the counter goes over some large number. When the counter goes above the large number we reset it to zero and also switch state.

This code is a bit odd, for example it does not start from any known state when it comes to s or counter. What could be added is a reset signal

and some logic associated with the reset that sets s to for example the Off state and sets counter to 0. My feeling is that it wont matter much in this case, as no matter what s and counter is initially it will sort itself out in a moment. This is of course no assumption you can make in general!

We have VHDL code with signals clk and led but nothing that tells vivado how those signals relate to clock generation or IO on the FPGA. To fix this we must create a constraints file that makes these connections from VHDL concepts to corresponding functionality on the FPGA.

Task: In the Sources pane of the Project Manager right click and select Add Sources. Check the Add or create constraints radio-button. and click next. Now click the Create File button and a dialog pops up that asks you to provide a name for a file of type .XDC. I just call the file constraints and click ok. Then click Finish in the Add or Create Constraints dialog.

The first line sets a timing constraints that tells the system we want the design to run at 100MHz (period 10ns). You can also tweak the clocks duty cycle and phase by adjusting the waveform parameters.

The next line states that something called package pin E3 should be connected to the VHDL signal clk. The package pins and their meaning can be found in the reference manual provided by the board manufacturer. In this case E3 is associated with clocking resources.

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