SSA register allocation question to AMD64

[David Chase]

I'm working on FP sub and div, they are not symmetric, and there is not a handy negate (that I can find) for either of these.

Instructions are 2-address, I have to map

  x = y OP z

onto

 x = x OP z

But if x == z, I am forced to either shuffle registers (what do I use for a spare?)

or clobber y, then move it it x (seems like this is not allowed).

Suggestions?

David

[Keith Randall]

Yes, this is tricky.

For now, you could declare that these instructions clobber X15 (the new regalloc, once it is in, does clobbering correctly) and then you can use X15 as a spare register if you need it.

Longer term, we need to teach regalloc about 2-address instructions, both symmetric and not.

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[Keith Randall]

For subtract, you can negate by xoring with the correct bit pattern, then add.  You'd have to declare a global variable with that bit pattern.

[David Chase]

Is that safe in the face of NaNs?

Or do I get extra cute and do a CMP[UN]ORDSS to generate yet another clever bit pattern?  But that would take a register anyway...

And clobbers looks like this?

fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},

clobbers: []regmask{x15}, outputs: []regMask{fp &^ x15}}

[Keith Randall]

On Fri, Aug 14, 2015 at 1:58 PM, David Chase <drc...@google.com> wrote:

Is that safe in the face of NaNs?

I believe so, as long as the only use of your negated value is an fadd.

 

Or do I get extra cute and do a CMP[UN]ORDSS to generate yet another clever bit pattern?  But that would take a register anyway...

And clobbers looks like this?

fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},

clobbers: []regmask{x15}, outputs: []regMask{fp &^ x15}}

Yes, that looks fine.