Attention is currently required from: Cherry Mui, M Zhuo, Mark Ryan.
Joel Sing would like Mark Ryan, M Zhuo and Cherry Mui to review this change.
cmd/compile/internal/riscv64: use CNOP for compiler inserted NOPs
This simplifies code generation, while also being a compressed
instruction that results in smaller code size.
Change-Id: I24258353688554042c2a836deed4830cc673e985
---
M src/cmd/compile/internal/riscv64/gsubr.go
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/src/cmd/compile/internal/riscv64/gsubr.go b/src/cmd/compile/internal/riscv64/gsubr.go
index 74bccf8..ee05963 100644
--- a/src/cmd/compile/internal/riscv64/gsubr.go
+++ b/src/cmd/compile/internal/riscv64/gsubr.go
@@ -11,10 +11,5 @@
)
func ginsnop(pp *objw.Progs) *obj.Prog {
- // Hardware nop is ADD $0, ZERO
- p := pp.Prog(riscv.AADD)
- p.From.Type = obj.TYPE_CONST
- p.Reg = riscv.REG_ZERO
- p.To = obj.Addr{Type: obj.TYPE_REG, Reg: riscv.REG_ZERO}
- return p
+ return pp.Prog(riscv.ACNOP)
}
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Joel SingThis would require compressed instructions in any RISC-V host running Go, so let's hold off on that until we have an accepted proposal to do so.
Proposal has been accepted, removing hold.
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Compress = flag.Bool("compress", true, "use compressed instructions (if supported by architecture)")Do you need both this and `CompressInstructions` below?
if compress && p.Mark&(NEED_PCREL_ITYPE_RELOC|NEED_PCREL_STYPE_RELOC|NEED_GOT_PCREL_ITYPE_RELOC) == 0 {Maybe define a named constant for a bit mask of all relocations, so if we add more relocations later it is unlikely to miss them. CALL and JAL relocations are not included because we don't compress CALL/JAL instructions? It doesn't seem to hurt if we include them as well.
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Provide a `compressedinstructions` compiler and assembler debug
flag, such that the compression pass can be disabled via
`-gcflags=all=-d=compressinstructions=0`.
Note that to completely disable compressed instructions I need to specify both asmflags and gcflags
```
-asmflags=all=-d=compressinstructions=0 -gcflags=all=-d=compressinstructions=0
```
If I just use gcflags, normal Go code is compiled without compressed instructions but hand coded assembly is still compressed. This might not be obvious to people (it wasn't to me initially) so we might need to document this somewhere.
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Looks pretty good in general. Just a few comments.
if ins.rd != REG_X0 && ins.rd == ins.rs1 {I think we need to check the imm here as well as rd0. The spec says
```
The C.SLLI code points with shamt=0 or with rd=x0 are HINTs.
```
So we shouldn't compress
```
SLLI $0, X10, X10
```
for example. Currently we do. I checked with binutils and it does not compress this instruction.
case ASRLI:The C.SRLI code points with shamt=0 are HINTs.
if ins.rd != REG_X0 && ins.rd == ins.rs1 && ins.rs2 != REG_X0 {We could compress ADD X10, X0, X11. binutils does seem to compress this to a c.mv. However, this sequence should be very uncommon in Go as one should normally write MOV X10, X11, which turns into a ADDI and so does get compressed. So maybe not worth the extra code.
case AAND:We're missing CANDI here. ANDI is fairly common so if we compress it we might save a few more bytes.
Provide a `compressedinstructions` compiler and assembler debug
flag, such that the compression pass can be disabled via
`-gcflags=all=-d=compressinstructions=0`.
Note that to completely disable compressed instructions I need to specify both asmflags and gcflags
```
-asmflags=all=-d=compressinstructions=0 -gcflags=all=-d=compressinstructions=0
```If I just use gcflags, normal Go code is compiled without compressed instructions but hand coded assembly is still compressed. This might not be obvious to people (it wasn't to me initially) so we might need to document this somewhere.
I've updated the RISC-V assembler documentation patch to mention the compressed instruction set and these two debug options.