[arch] riscv64: add support for Zicond instructions
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Commit message
riscv64: add support for Zicond instructions
Add support for the dissassembly of Zicond instructions and test cases.
Change diff
diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go
index 18c9fbf..2a951f9 100644
--- a/riscv64/riscv64asm/tables.go
+++ b/riscv64/riscv64asm/tables.go
@@ -116,6 +116,8 @@
CSRRWI
CTZ
CTZW
+ CZERO_EQZ
+ CZERO_NEZ
C_ADD
C_ADDI
C_ADDI16SP
@@ -1110,6 +1112,8 @@
CSRRWI: "CSRRWI",
CTZ: "CTZ",
CTZW: "CTZW",
+ CZERO_EQZ: "CZERO.EQZ",
+ CZERO_NEZ: "CZERO.NEZ",
C_ADD: "C.ADD",
C_ADDI: "C.ADDI",
C_ADDI16SP: "C.ADDI16SP",
@@ -2211,6 +2215,10 @@
{mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}},
// CTZW rd, rs1
{mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}},
+ // CZERO.EQZ rd, rs1, rs2
+ {mask: 0xfe00707f, value: 0x0e005033, op: CZERO_EQZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
+ // CZERO.NEZ rd, rs1, rs2
+ {mask: 0xfe00707f, value: 0x0e007033, op: CZERO_NEZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
// C.ADD rd_rs1_n0, c_rs2_n0
{mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}},
// C.ADDI rd_rs1_n0, c_nzimm6
diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt
index 56139a9..9343cb0 100644
--- a/riscv64/riscv64asm/testdata/gnucases.txt
+++ b/riscv64/riscv64asm/testdata/gnucases.txt
@@ -384,6 +384,10 @@
8624| fld f9,64(x2)
3eb0| fsd f15,32(x2)
+# 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
+b353530e| czero.eqz x7,x6,x5
+b373530e| czero.nez x7,x6,x5
+
# "V" Standard Extension for Vector Operations, Version 1.0
# 31.6: Configuration Setting Instructions
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt
index 8131764..fba383a 100644
--- a/riscv64/riscv64asm/testdata/plan9cases.txt
+++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -334,6 +334,10 @@
b3115228| BSET X5, X4, X3
1393f32b| BSETI $63, X7, X6
+# 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
+b353530e| CZEROEQZ X5, X6, X7
+b373530e| CZERONEZ X5, X6, X7
+
# "V" Standard Extension for Vector Operations, Version 1.0
# 31.6: Configuration Setting Instructions
diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go
index 0434337..26845a5 100644
--- a/riscv64/riscv64spec/spec.go
+++ b/riscv64/riscv64spec/spec.go
@@ -36,6 +36,7 @@
"rv_zbb",
"rv_zbs",
"rv_zfh",
+ "rv_zicond",
"rv_zicsr",
"rv_zifencei",
"rv64_a",
@@ -171,7 +172,7 @@
func genInst(words []string) {
op := strings.ToUpper(strings.Replace(words[0], ".", "_", -1))
- opstr := fmt.Sprintf("%s:\t\"%s\",", op, strings.ToUpper(words[0]))
+ opstr := fmt.Sprintf("%-18s %q,", op+":", strings.ToUpper(words[0]))
var value uint32
var mask uint32
@@ -207,7 +208,7 @@
// Re-generate the opcode string, opcode value and mask.
for i, suf := range suffix {
aop := op + strings.Replace(suf, ".", "_", -1)
- aopstr := fmt.Sprintf("%s:\t\"%s\",", aop, strings.ToUpper(words[0])+suf)
+ aopstr := fmt.Sprintf("%-18s %q,", aop+":", strings.ToUpper(words[0])+suf)
avalue := value | (uint32(i) << 25)
amask := mask | 0x06000000
ainstFormatComment := "// " + strings.Replace(aop, "_", ".", -1) + " " + strings.Replace(instArgsStr, "arg_", "", -1)
@@ -243,7 +244,7 @@
for i := uint32(2); i <= 8; i++ {
segName := strings.ToUpper(fmt.Sprintf("%sSEG%d%s", segOpPrefix, i, segOpSuffix))
segOp := strings.Replace(segName, ".", "_", -1)
- segOpStr := fmt.Sprintf("%s:\t\"%s\",", segOp, segName)
+ segOpStr := fmt.Sprintf("%-18s %q,", segOp+":", segName)
segValue := value | (i-1)<<29
instFormatComment := "// " + segName + " " + strings.Replace(instArgsStr, "arg_", "", -1)
instFormat := fmt.Sprintf("{mask: %#08x, value: %#08x, op: %s, args: argTypeList{%s}},", mask, segValue, segOp, instArgsStr)
Change information
- M riscv64/riscv64asm/tables.go
- M riscv64/riscv64asm/testdata/gnucases.txt
- M riscv64/riscv64asm/testdata/plan9cases.txt
- M riscv64/riscv64spec/spec.go
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Gopher Robot (Gerrit)
Gopher Robot added 1 comment![]( "Open in Gerrit")
I spotted some possible problems with your PR:
1. You usually need to reference a bug number for all but trivial or cosmetic fixes. For the arch repo, the format is usually 'Fixes golang/go#12345' or 'Updates golang/go#12345' at the end of the commit message. Should you have a bug reference?
Please address any problems by updating the GitHub PR.
When complete, mark this comment as 'Done' and click the [blue 'Reply' button](https://go.dev/wiki/GerritBot#i-left-a-reply-to-a-comment-in-gerrit-but-no-one-but-me-can-see-it) above. These findings are based on heuristics; if a finding does not apply, briefly reply here saying so.
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Mark Ryan (Gerrit)
Mark Ryan added 2 comments![]( "Open in Gerrit")
The commit message needs to be line wrapped at 70 columns.
Also the tests fails on a riscv64 device with objdump installed. The issue here is that objdumpext_test.go needs to be update to include Zicond in the .riscv.attributes section of the generated test binaries. Note the last person to update objdumpext_test.go was me, and it looks like I didn't do this correctly. I added v1p0_ but I didn't update the lengths. It was just luck it worked. So we need to add zicond1p0_ to the string and update the lengths by 15, 10 for zicond1p0_ and 5 for v1p0_ that I forgot to add in https://go-review.googlesource.com/c/arch/+/670876.
Locally, this works for me
```
@@ -277,7 +277,7 @@ func writeELF64(f *os.File, size int) error {
Type: uint32(0x70000003), // SHT_RISCV_ATTRIBUTES
Addr: 0,
Off: uint64(off2 + (off3-off2)*4 + strtabsize),
- Size: 114,
+ Size: 129,
Addralign: 1,
}
binary.Write(&buf, binary.LittleEndian, §)
@@ -293,7 +293,7 @@ func writeELF64(f *os.File, size int) error {
buf.WriteString("\x00.text\x00.riscv.attributes\x00.shstrtab\x00")
// Contents of .riscv.attributes section
// which specify the extension and priv spec version. (1.11)
- buf.WriteString("Aq\x00\x00\x00riscv\x00\x01g\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
+ buf.WriteString("A\x80\x00\x00\x00riscv\x00\x01\x76\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zicond1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
f.Write(buf.Bytes())
return nil
}
```
@mengzh...@gmail.com do you know what the procedure for updating this string is? Do we just do it manually, or do we pull it out of some compiled C binary.
aopstr := fmt.Sprintf("%-18s %q,", aop+":", strings.ToUpper(words[0])+suf)I'm not sure it's worth trying to get the spacing right here here, as we need to run go fmt on the generate tables.go before copying it into riscv64asm folder. This will override all your custom formatting.
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Meng Zhuo (Gerrit)
Meng Zhuo added 1 comment![]( "Open in Gerrit")
The commit message needs to be line wrapped at 70 columns.
Also the tests fails on a riscv64 device with objdump installed. The issue here is that objdumpext_test.go needs to be update to include Zicond in the .riscv.attributes section of the generated test binaries. Note the last person to update objdumpext_test.go was me, and it looks like I didn't do this correctly. I added v1p0_ but I didn't update the lengths. It was just luck it worked. So we need to add zicond1p0_ to the string and update the lengths by 15, 10 for zicond1p0_ and 5 for v1p0_ that I forgot to add in https://go-review.googlesource.com/c/arch/+/670876.
Locally, this works for me
```
@@ -277,7 +277,7 @@ func writeELF64(f *os.File, size int) error {
Type: uint32(0x70000003), // SHT_RISCV_ATTRIBUTES
Addr: 0,
Off: uint64(off2 + (off3-off2)*4 + strtabsize),
- Size: 114,
+ Size: 129,
Addralign: 1,
}
binary.Write(&buf, binary.LittleEndian, §)
@@ -293,7 +293,7 @@ func writeELF64(f *os.File, size int) error {
buf.WriteString("\x00.text\x00.riscv.attributes\x00.shstrtab\x00")
// Contents of .riscv.attributes section
// which specify the extension and priv spec version. (1.11)
- buf.WriteString("Aq\x00\x00\x00riscv\x00\x01g\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
+ buf.WriteString("A\x80\x00\x00\x00riscv\x00\x01\x76\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zicond1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
f.Write(buf.Bytes())
return nil
}
```@mengzh...@gmail.com do you know what the procedure for updating this string is? Do we just do it manually, or do we pull it out of some compiled C binary.
If I recall correctly the attributes from the first commit is pull out of compiled C binary, which inspried my attrs CL.
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Xueqi Luo (Gerrit)
Xueqi Luo added 2 comments![]( "Open in Gerrit")
aopstr := fmt.Sprintf("%-18s %q,", aop+":", strings.ToUpper(words[0])+suf)I'm not sure it's worth trying to get the spacing right here here, as we need to run go fmt on the generate tables.go before copying it into riscv64asm folder. This will override all your custom formatting.
Done
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Meng Zhuo (Gerrit)
Meng Zhuo voted and added 3 comments![]( "Open in Gerrit")
Votes added by Meng Zhuo
| Commit-Queue | +1 |
3 comments
some nits, general LGTM.
By the way, @mark...@rivosinc.com I found that zfh already inclued in original attributes.
riscv64: add support for Zicond instructionsextra space.
Add support for the dissassembly of Zicond instructions and test cases.extra space
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Xueqi Luo (Gerrit)
Xueqi Luo added 3 comments![]( "Open in Gerrit")
riscv64: add support for Zicond instructionsXueqi Luoextra space.
Done
Add support for the dissassembly of Zicond instructions and test cases.Xueqi Luoextra space
Done
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Xueqi Luo (Gerrit)
Xueqi Luo added 1 comment![]( "Open in Gerrit")
Meng ZhuoThe commit message needs to be line wrapped at 70 columns.
Also the tests fails on a riscv64 device with objdump installed. The issue here is that objdumpext_test.go needs to be update to include Zicond in the .riscv.attributes section of the generated test binaries. Note the last person to update objdumpext_test.go was me, and it looks like I didn't do this correctly. I added v1p0_ but I didn't update the lengths. It was just luck it worked. So we need to add zicond1p0_ to the string and update the lengths by 15, 10 for zicond1p0_ and 5 for v1p0_ that I forgot to add in https://go-review.googlesource.com/c/arch/+/670876.
Locally, this works for me
```
@@ -277,7 +277,7 @@ func writeELF64(f *os.File, size int) error {
Type: uint32(0x70000003), // SHT_RISCV_ATTRIBUTES
Addr: 0,
Off: uint64(off2 + (off3-off2)*4 + strtabsize),
- Size: 114,
+ Size: 129,
Addralign: 1,
}
binary.Write(&buf, binary.LittleEndian, §)
@@ -293,7 +293,7 @@ func writeELF64(f *os.File, size int) error {
buf.WriteString("\x00.text\x00.riscv.attributes\x00.shstrtab\x00")
// Contents of .riscv.attributes section
// which specify the extension and priv spec version. (1.11)
- buf.WriteString("Aq\x00\x00\x00riscv\x00\x01g\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
+ buf.WriteString("A\x80\x00\x00\x00riscv\x00\x01\x76\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zicond1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b")
f.Write(buf.Bytes())
return nil
}
```@mengzh...@gmail.com do you know what the procedure for updating this string is? Do we just do it manually, or do we pull it out of some compiled C binary.
If I recall correctly the attributes from the first commit is pull out of compiled C binary, which inspried my attrs CL.
Hi @mark...@rivosinc.com @mengzh...@gmail.com
I've addressed your review comments and pushed a new patchset. Could you please take another look? Thanks!
Mark Ryan (Gerrit)
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Votes added by Mark Ryan
| Code-Review | +2 |
2 comments
LGTM. Tried this out locally and all the tests are passing now.
// RV64GC_zba_zbb_zbs Extensions ListingI note this comment is out of date, but it has been for some time. I think personally, we should just remove it. We can do this separately though. Doesn't need to be done in this patch.
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Mark Ryan (Gerrit)
Mark Ryan added 1 comment![]( "Open in Gerrit")
// RV64GC_zba_zbb_zbs Extensions ListingI note this comment is out of date, but it has been for some time. I think personally, we should just remove it. We can do this separately though. Doesn't need to be done in this patch.
Marked as resolved.
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| Code-Review | +2 |
1 comment
Add support for the dissassembly of Zicond instructions and test cases.```suggestion
Add support for the disassembly of Zicond instructions and test cases.
```
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Xueqi Luo (Gerrit)
Xueqi Luo added 1 comment![]( "Open in Gerrit")
Add support for the dissassembly of Zicond instructions and test cases.```suggestion
Add support for the disassembly of Zicond instructions and test cases.
```
Cood catch, thank you.
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Xueqi Luo (Gerrit)
Xueqi Luo added 1 comment![]( "Open in Gerrit")
I spotted some possible problems with your PR:
1. You usually need to reference a bug number for all but trivial or cosmetic fixes. For the arch repo, the format is usually 'Fixes golang/go#12345' or 'Updates golang/go#12345' at the end of the commit message. Should you have a bug reference?Please address any problems by updating the GitHub PR.
When complete, mark this comment as 'Done' and click the [blue 'Reply' button](https://go.dev/wiki/GerritBot#i-left-a-reply-to-a-comment-in-gerrit-but-no-one-but-me-can-see-it) above. These findings are based on heuristics; if a finding does not apply, briefly reply here saying so.
To update the commit title or commit message body shown here in Gerrit, you must edit the GitHub PR title and PR description (the first comment) in the GitHub web interface using the 'Edit' button or 'Edit' menu entry there. Note: pushing a new commit to the PR will not automatically update the commit message used by Gerrit.
For more details, see:
- [how to update commit messages](https://go.dev/wiki/GerritBot/#how-does-gerritbot-determine-the-final-commit-message) for PRs imported into Gerrit.
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Done
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Change information
riscv64: add support for Zicond instructions
Add support for the disassembly of Zicond instructions and test cases.
- M riscv64/riscv64asm/objdumpext_test.go
- M riscv64/riscv64asm/tables.go
- M riscv64/riscv64asm/testdata/gnucases.txt
- M riscv64/riscv64asm/testdata/plan9cases.txt
- M riscv64/riscv64spec/spec.go
Code-Review: +1 by Michael Pratt, +1 by Dmitri Shuralyov, +2 by Mark Ryan, +2 by Meng Zhuo, +2 by Joel Sing
TryBots-Pass: LUCI-TryBot-Result+1 by Go LUCI
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