[go] cmd/asm, cmd/internal/obj: add crypto algorithm suites for riscv64

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cmd/asm, cmd/internal/obj: add crypto algorithm suites for riscv64

This CL adds crypto algorithm suites' intrinsic encoding and testcase:

* Zvkg - Vector GCM/GMAC
* Zvkned - NIST Suite: Vector AES Block Cipher
* Zvknh[ab] - NIST Suite: Vector SHA-2 Secure Hash
* Zvksed - ShangMi Suite: SM4 Block Cipher
* Zvksh - ShangMi Suite: SM3 Secure Hash
Change-Id: I0d841cce0fd734c28e409d6b6edbcfdc0c7da9d4

Change diff

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 2d0250d..e916b1f 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -983,6 +983,37 @@
 	VRORVI		$16, V2, V3			// d7312852
 	VRORVI		$16, V2, V0, V3			// d7312850
 
+	// Zvkg - Vector GCM/GMAC
+	VGHSHVV		V1, V2, V3			// f7a120b2
+	VGMULVV		V1, V2				// 77a118a2
+
+	// Zvkned - NIST Suite: Vector AES Block Cipher
+	VAESEFVV	V1, V2				// 77a111a2
+	VAESEFVS	V1, V2				// 77a111a6
+	VAESEMVV	V1, V2				// 772111a2
+	VAESEMVS	V1, V2				// 772111a6
+	VAESDFVV	V1, V2				// 77a110a2
+	VAESDFVS	V1, V2				// 77a110a6
+	VAESDMVV	V1, V2				// 772110a2
+	VAESDMVS	V1, V2				// 772110a6
+	VAESKF1VI	$16, V2, V3			// f721288a
+	VAESKF2VI	$16, V2, V3			// f72128aa
+	VAESZVS		V1, V2				// 77a113a6
+
+	// Zvknh[ab] - NIST Suite: Vector SHA-2 Secure Hash
+	VSHA2MSVV	V1, V2, V3			// f7a120b6
+	VSHA2CHVV	V1, V2, V3			// f7a120ba
+	VSHA2CLVV	V1, V2, V3			// f7a120be
+
+	// Zvksed - ShangMi Suite: SM4 Block Cipher
+	VSM4KVI		$16, V2, V3			// f7212886
+	VSM4RVV		V1, V2				// 772118a2
+	VSM4RVS		V1, V2				// 772118a6
+
+	// Zvksh - ShangMi Suite: SM3 Secure Hash
+	VSM3MEVV	V1, V2, V3			// f7a12082
+	VSM3CVI		$16, V2, V3			// f72128ae
+
 	//
 	// Privileged ISA
 	//
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index e54c4e2..e086fb9 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -2480,6 +2480,37 @@
 	AVRORVX & obj.AMask: {enc: rVIVEncoding},
 	AVRORVI & obj.AMask: {enc: rVVuEncoding},
 
+	// Zvkg - Vector GCM/GMAC
+	AVGHSHVV & obj.AMask: {enc: rVVVEncoding},
+	AVGMULVV & obj.AMask: {enc: rVVEncoding},
+
+	// Zvkned - NIST Suite: Vector AES Block Cipher
+	AVAESEFVV & obj.AMask:  {enc: rVVEncoding},
+	AVAESEFVS & obj.AMask:  {enc: rVVEncoding},
+	AVAESEMVV & obj.AMask:  {enc: rVVEncoding},
+	AVAESEMVS & obj.AMask:  {enc: rVVEncoding},
+	AVAESDFVV & obj.AMask:  {enc: rVVEncoding},
+	AVAESDFVS & obj.AMask:  {enc: rVVEncoding},
+	AVAESDMVV & obj.AMask:  {enc: rVVEncoding},
+	AVAESDMVS & obj.AMask:  {enc: rVVEncoding},
+	AVAESKF1VI & obj.AMask: {enc: rVVuEncoding},
+	AVAESKF2VI & obj.AMask: {enc: rVVuEncoding},
+	AVAESZVS & obj.AMask:   {enc: rVVEncoding},
+
+	// Zvknh[ab] - NIST Suite: Vector SHA-2 Secure Hash
+	AVSHA2MSVV & obj.AMask: {enc: rVVVEncoding},
+	AVSHA2CHVV & obj.AMask: {enc: rVVVEncoding},
+	AVSHA2CLVV & obj.AMask: {enc: rVVVEncoding},
+
+	// Zvksed - ShangMi Suite: SM4 Block Cipher
+	AVSM4KVI & obj.AMask: {enc: rVVuEncoding},
+	AVSM4RVV & obj.AMask: {enc: rVVEncoding},
+	AVSM4RVS & obj.AMask: {enc: rVVEncoding},
+
+	// Zvksh - ShangMi Suite: SM3 Secure Hash
+	AVSM3MEVV & obj.AMask: {enc: rVVVEncoding},
+	AVSM3CVI & obj.AMask:  {enc: rVVuEncoding},
+
 	//
 	// Privileged ISA
 	//
@@ -3520,7 +3551,7 @@
 		}
 		ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), obj.REG_NONE
 
-	case AVMADCVV, AVMADCVX, AVMSBCVV, AVMSBCVX, AVMADCVI:
+	case AVMADCVV, AVMADCVX, AVMSBCVV, AVMSBCVX, AVMADCVI, AVGHSHVV:
 		ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)
 
 	case AVNEGV, AVWCVTXXV, AVWCVTUXXV, AVNCVTXXW:
@@ -3593,6 +3624,25 @@
 			ins.as = AVMSGTUVI
 		}
 		ins.rd, ins.rs1, ins.rs2, ins.rs3, ins.imm = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE, ins.imm-1
+
+	case AVAESKF1VI, AVAESKF2VI, AVSM4KVI, AVSM3CVI:
+		if ins.rs3 != obj.REG_NONE {
+			p.Ctxt.Diag("%v: too many operands for instruction", p)
+		}
+		ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE
+
+	case AVGMULVV, AVAESEFVV, AVAESEFVS, AVAESEMVV, AVAESEMVS, AVAESDFVV, AVAESDFVS, AVAESDMVV,
+		AVAESDMVS, AVAESZVS, AVSM4RVV, AVSM4RVS:
+		if ins.rs3 != obj.REG_NONE {
+			p.Ctxt.Diag("%v: too many operands for instruction", p)
+		}
+		ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), obj.REG_NONE, uint32(p.From.Reg)
+
+	case AVSHA2MSVV, AVSHA2CHVV, AVSHA2CLVV, AVSM3MEVV:
+		if ins.rs3 != obj.REG_NONE {
+			p.Ctxt.Diag("%v: too many operands for instruction", p)
+		}
+		ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)
 	}
 
 	for _, ins := range inss {

Change information

Files:
  • M src/cmd/asm/internal/asm/testdata/riscv64.s
  • M src/cmd/internal/obj/riscv/obj.go
Change size: M
Delta: 2 files changed, 82 insertions(+), 1 deletion(-)
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@jo...@sing.id.au I had merged two CLs, PTAL, thanks

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      Joel Sing (Gerrit)

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      Patchset-level comments
      File-level comment, Patchset 9 (Latest):
      Joel Sing . resolved

      There is hardware that exists that implements these extensions, hence no objection to adding support.

      File src/cmd/asm/internal/asm/testdata/riscv64.s
      Line 2049, Patchset 9 (Latest): // 32.2.7: hangMi Suite: SM4 Block Cipher
      Joel Sing . unresolved
      ```suggestion
      	// 32.2.7: ShangMi Suite: SM4 Block Cipher
      ```
      File src/cmd/asm/internal/asm/testdata/riscv64validation.s
      Line 604, Patchset 9 (Latest): VAESKF1VI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]"
      Joel Sing . unresolved

      Would be good to also add the $-1 versions of these.

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        File src/cmd/asm/internal/asm/testdata/riscv64.s
        Line 2049, Patchset 9: // 32.2.7: hangMi Suite: SM4 Block Cipher
        Joel Sing . resolved
        ```suggestion
        	// 32.2.7: ShangMi Suite: SM4 Block Cipher
        ```
        Meng Zhuo

        Done

        File src/cmd/asm/internal/asm/testdata/riscv64validation.s
        Line 604, Patchset 9: VAESKF1VI $32, V2, V3 // ERROR "unsigned immediate 32 must be in range [0, 31]"
        Joel Sing . resolved

        Would be good to also add the $-1 versions of these.

        Meng Zhuo

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          Meng Zhuo . resolved

          retry to eliminate unrelated failure.

          File-level comment, Patchset 14 (Latest):
          Meng Zhuo . resolved

          Retry to eliminate unrelated failure.

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          Joel Sing (Gerrit)

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          Joel Sing . unresolved

          Change looks good, however we're missing cmd/asm/internal/asm/testdata/riscv64cmd/asm/internal/asm/testdata/riscv64error.s changes.

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            Meng Zhuo uploaded patch set #15 to this change.
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              Meng Zhuo (Gerrit)

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              Meng Zhuo (Gerrit)

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              Patchset-level comments

              Change looks good, however we're missing cmd/asm/internal/asm/testdata/riscv64cmd/asm/internal/asm/testdata/riscv64error.s changes.

              Meng Zhuo

              Ah,Thanks, I've forget to rebase on the right CL.

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                Julian Zhu (Gerrit)

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                Julian Zhu voted Code-Review+2

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