[go] cmd/internal/obj/riscv: add assembly support for CMO instructions

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Boyao Wang (Gerrit)

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Sep 11, 2025, 4:11:15 AMSep 11
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cmd/internal/obj/riscv: add assembly support for CMO instructions

Add assembly support for cache-management instructions, which are defined in chapter 19 of RISC-V ISA manual.
Change-Id: I7e64951d5d20306f02f8bf2005bc9b299c12f0ca

Change diff

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 75abcef..6b58982 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -220,6 +220,26 @@
 	AMOMINUW	X5, (X6), X7			// af2353c6
 	AMOMINUD	X5, (X6), X7			// af3353c6
 
+	//
+	// "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0
+	//
+
+	// 19.6.1: Zicbom - Cache-Block Management Instructions
+	CBOCLEAN	(X5)				// 0fa01200
+	CBOFLUSH	(X6)				// 0f202300
+	CBOINVAL	(X7)				// 0fa00300
+
+	// 19.6.2: Zicboz - Cache-Block Zero Instructions
+	CBOZERO		(X5)				// 0fa04200
+
+	// 19.6.3: Zicbop - Cache-Block Prefetch Instructions
+	PREFETCHI	-2048(X5)			// 13e00280
+	PREFETCHI	2016(X5)			// 13e0027e
+	PREFETCHR	-2048(X6)			// 13601380
+	PREFETCHR	2016(X6)			// 1360137e
+	PREFETCHW	-2048(X7)			// 13e03380
+	PREFETCHW	2016(X7)			// 13e0337e
+
 	// 20.5: Single-Precision Load and Store Instructions
 	FLW	(X5), F0				// 07a00200
 	FLW	4(X5), F0				// 07a04200
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index f0be8f6..9bbe795 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -96,6 +96,13 @@
 	"AMOMAXUW",
 	"AMOMINW",
 	"AMOMINUW",
+	"CBOCLEAN",
+	"CBOFLUSH",
+	"CBOINVAL",
+	"CBOZERO",
+	"PREFETCHI",
+	"PREFETCHR",
+	"PREFETCHW",
 	"FLW",
 	"FSW",
 	"FADDS",
diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 116ccb4..4b8b53e 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -450,6 +450,23 @@
 	AAMOMINW
 	AAMOMINUW
 
+	//
+	// "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0
+	//
+
+	// 19.6.1: Zicbom - Cache-Block Management Instructions
+	ACBOCLEAN
+	ACBOFLUSH
+	ACBOINVAL
+
+	// 19.6.2: Zicboz - Cache-Block Zero Instructions
+	ACBOZERO
+
+	// 19.6.3: Zicbop - Cache-Block Prefetch Instructions
+	APREFETCHI
+	APREFETCHR
+	APREFETCHW
+
 	// 20.5: Single-Precision Load and Store Instructions
 	AFLW
 	AFSW
diff --git a/src/cmd/internal/obj/riscv/inst.go b/src/cmd/internal/obj/riscv/inst.go
index 16f2272..d7e67a6 100644
--- a/src/cmd/internal/obj/riscv/inst.go
+++ b/src/cmd/internal/obj/riscv/inst.go
@@ -1,4 +1,4 @@
-// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
+// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr rv_zicbo; DO NOT EDIT.
 package riscv
 
 import "cmd/internal/obj"
@@ -170,6 +170,14 @@
 		return &inst{0x2, 0x4, 0x1, 0x0, 0, 0x0}
 	case ACXOR:
 		return &inst{0x21, 0x0, 0x1, 0x0, 0, 0x0}
+	case ACBOCLEAN:
+		return &inst{0xf, 0x2, 0x0, 0x1, 1, 0x0}
+	case ACBOFLUSH:
+		return &inst{0xf, 0x2, 0x0, 0x2, 2, 0x0}
+	case ACBOINVAL:
+		return &inst{0xf, 0x2, 0x0, 0x0, 0, 0x0}
+	case ACBOZERO:
+		return &inst{0xf, 0x2, 0x0, 0x4, 4, 0x0}
 	case ACLZ:
 		return &inst{0x13, 0x1, 0x0, 0x0, 1536, 0x30}
 	case ACLZW:
@@ -448,6 +456,12 @@
 		return &inst{0x13, 0x6, 0x0, 0x0, 0, 0x0}
 	case AORN:
 		return &inst{0x33, 0x6, 0x0, 0x0, 1024, 0x20}
+	case APREFETCHI:
+		return &inst{0x13, 0x6, 0x0, 0x0, 0, 0x0}
+	case APREFETCHR:
+		return &inst{0x13, 0x6, 0x0, 0x1, 1, 0x0}
+	case APREFETCHW:
+		return &inst{0x13, 0x6, 0x0, 0x3, 3, 0x0}
 	case AREM:
 		return &inst{0x33, 0x6, 0x0, 0x0, 32, 0x1}
 	case AREMU:
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index 40f143b..79f4dc0 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -2007,6 +2007,23 @@
 	AFLD & obj.AMask: {enc: iFEncoding},
 	AFSD & obj.AMask: {enc: sFEncoding},
 
+	//
+	// "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0
+	//
+
+	// 19.6.1: Zicbom - Cache-Block Management Instructions
+	ACBOCLEAN & obj.AMask: {enc: iIIEncoding},
+	ACBOFLUSH & obj.AMask: {enc: iIIEncoding},
+	ACBOINVAL & obj.AMask: {enc: iIIEncoding},
+
+	// 19.6.3: Zicboz - Cache-Block Zero Instructions
+	ACBOZERO & obj.AMask: {enc: iIIEncoding},
+
+	// 19.6.2: Zicbop - Cache-Block Prefetch Instructions
+	APREFETCHI & obj.AMask: {enc: iIIEncoding},
+	APREFETCHR & obj.AMask: {enc: iIIEncoding},
+	APREFETCHW & obj.AMask: {enc: iIIEncoding},
+
 	// 21.4: Double-Precision Floating-Point Computational Instructions
 	AFADDD & obj.AMask:   {enc: rFFFEncoding},
 	AFSUBD & obj.AMask:   {enc: rFFFEncoding},
@@ -3327,6 +3344,17 @@
 			ins.imm = -1022
 		}
 
+	case ACBOCLEAN, ACBOFLUSH, ACBOINVAL, ACBOZERO:
+		insEnc := encode(p.As)
+		ins.rs1 = ins.rd
+		ins.rd = REG_ZERO
+		ins.imm = insEnc.csr
+
+	case APREFETCHI, APREFETCHR, APREFETCHW:
+		ins.rs1 = ins.rd
+		ins.rd = REG_ZERO
+		ins.imm = p.To.Offset
+
 	case AFENCE:
 		ins.rd, ins.rs1, ins.rs2 = REG_ZERO, REG_ZERO, obj.REG_NONE
 		ins.imm = 0x0ff

Change information

Files:
  • M src/cmd/asm/internal/asm/testdata/riscv64.s
  • M src/cmd/internal/obj/riscv/anames.go
  • M src/cmd/internal/obj/riscv/cpu.go
  • M src/cmd/internal/obj/riscv/inst.go
  • M src/cmd/internal/obj/riscv/obj.go
Change size: M
Delta: 5 files changed, 87 insertions(+), 1 deletion(-)
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