[go/dev.simd] [dev.simd] simdgen: detect SetElem greg width from element width

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Alexander Musman (Gerrit)

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Mar 8, 2026, 7:37:27 AMMar 8
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[dev.simd] simdgen: detect SetElem greg width from element width
Change-Id: I9b448e4f5c579c0f99d367ce9f5be8973c408d98

Change diff

diff --git a/src/simd/archsimd/_gen/simdgen/arm64/operands.go b/src/simd/archsimd/_gen/simdgen/arm64/operands.go
index c827710..845fe8a 100644
--- a/src/simd/archsimd/_gen/simdgen/arm64/operands.go
+++ b/src/simd/archsimd/_gen/simdgen/arm64/operands.go
@@ -118,6 +118,9 @@
 				op.Bits = 32
 			}
 		}
+		if mnemonic == "INS" {
+			op.Bits = arrangement.elemBits
+		}
 	case OperandVElem, OperandList:
 		panic("expected this operand type to be early-lowered")
 	}
diff --git a/src/simd/archsimd/_gen/simdgen/arm64/operands_test.go b/src/simd/archsimd/_gen/simdgen/arm64/operands_test.go
index 1d3c2ec..1be377f 100644
--- a/src/simd/archsimd/_gen/simdgen/arm64/operands_test.go
+++ b/src/simd/archsimd/_gen/simdgen/arm64/operands_test.go
@@ -89,6 +89,18 @@
 			wantListNums:  []int{-1, -1, -1, -1, -1},
 		},
 		{
+			name:          "INS general register to element - from ins_advsimd_gen.xml",
+			template:      "INS  <Vd>.4S[<index1>], <Wn>",
+			resultInArg0:  false, // VElem dest automatically sets resultInArg0
+			wantTokenText: []string{"<Vd>.4S[<index1>]", "<Wn>"},
+			wantTypes:     []OperandType{OperandVElem, OperandGReg},
+			wantIsDest:    []bool{true, false},
+			wantCount:     4,
+			wantClasses:   []string{"vreg", "immediate", "vreg", "greg"},
+			wantNames:     []string{"destination", "destination_i", "original", "x"},
+			wantListNums:  []int{-1, -1, -1, -1},
+		},
+		{
 			name:          "UMOV to general register - from umov_advsimd.xml",
 			template:      "UMOV  <Wd>, <Vn>.4S[<index>]",
 			resultInArg0:  false,
@@ -167,3 +179,75 @@
 		})
 	}
 }
+
+// TestOperandInstantiateBits tests that Instantiate sets Bits correctly for INS greg operands.
+func TestOperandInstantiateBits(t *testing.T) {
+	tests := []struct {
+		name        string
+		mnemonic    string
+		arrangement Arrangement
+		wantBits    int
+	}{
+		{
+			name:     "INS 16B element - 8-bit greg",
+			mnemonic: "INS",
+			arrangement: Arrangement{
+				arrangement: "16B",
+				bits:        128,
+				elemBits:    8,
+				lanes:       16,
+				baseType:    "uint",
+			},
+			wantBits: 8,
+		},
+		{
+			name:     "INS 8H element - 16-bit greg",
+			mnemonic: "INS",
+			arrangement: Arrangement{
+				arrangement: "8H",
+				bits:        128,
+				elemBits:    16,
+				lanes:       8,
+				baseType:    "uint",
+			},
+			wantBits: 16,
+		},
+		{
+			name:     "INS 4S element - 32-bit greg",
+			mnemonic: "INS",
+			arrangement: Arrangement{
+				arrangement: "4S",
+				bits:        128,
+				elemBits:    32,
+				lanes:       4,
+				baseType:    "uint",
+			},
+			wantBits: 32,
+		},
+		{
+			name:     "INS 2D element - 64-bit greg",
+			mnemonic: "INS",
+			arrangement: Arrangement{
+				arrangement: "2D",
+				bits:        128,
+				elemBits:    64,
+				lanes:       2,
+				baseType:    "uint",
+			},
+			wantBits: 64,
+		},
+	}
+
+	for _, tt := range tests {
+		t.Run(tt.name, func(t *testing.T) {
+			op := &Operand{
+				Type:       OperandGReg,
+				Class:      "greg",
+				Name:       "x",
+				ListNumber: -1,
+			}
+			op.Instantiate(tt.arrangement, DefaultArngs, 1, tt.mnemonic)
+			requireEqual(t, tt.wantBits, op.Bits)
+		})
+	}
+}

Change information

Files:
  • M src/simd/archsimd/_gen/simdgen/arm64/operands.go
  • M src/simd/archsimd/_gen/simdgen/arm64/operands_test.go
Change size: M
Delta: 2 files changed, 87 insertions(+), 0 deletions(-)
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Alexander Musman (Gerrit)

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Mar 8, 2026, 7:43:31 AMMar 8
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Alexander Musman . resolved

This is a helper change for SetElem/GetElem.

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