[arch] riscv64: add Zawrs disassembly support

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Kinson Nee (Gerrit)

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Jul 16, 2026, 1:54:15 AMJul 16

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riscv64: add Zawrs disassembly support

Add decoding and syntax tests for the Zawrs wait-on-reservation-set
instructions, wrs.nto and wrs.sto.

The instructions are included in the riscv-opcodes extension list, the
generated decoder table, GNU and Plan 9 syntax testdata, and the objdump
extension attributes. Also allow old objdump versions that predate Zawrs
support to print the instructions as .4byte.

Co-authored-by: YuanSheng <yuan...@isrc.iscas.ac.cn>

Change-Id: I75ec02552f3bff60075cef4fa850d4f5fc5e8c98

Change diff

diff --git a/riscv64/riscv64asm/objdump_test.go b/riscv64/riscv64asm/objdump_test.go
index ddaa28c..be37035 100644
--- a/riscv64/riscv64asm/objdump_test.go
+++ b/riscv64/riscv64asm/objdump_test.go
@@ -88,6 +88,11 @@
 		return true
 	}
 
+	// Zawrs instructions are supported by objdump 2.40 and later.
+	if strings.HasPrefix(dec.text, ".4byte") && (inst.Op == WRS_NTO || inst.Op == WRS_STO) && !objdumpVersionAtLeast(version, "2.40") {
+		return true
+	}
+
 	return false
 }
 
diff --git a/riscv64/riscv64asm/objdumpext_test.go b/riscv64/riscv64asm/objdumpext_test.go
index acbd925..5cbace3 100644
--- a/riscv64/riscv64asm/objdumpext_test.go
+++ b/riscv64/riscv64asm/objdumpext_test.go
@@ -289,7 +289,7 @@
 	strtabsize := len("\x00.text\x00.riscv.attributes\x00.shstrtab\x00")
 	// RISC-V objdump needs the .riscv.attributes section to identify extensions.
 	exts := "rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_" +
-		"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zmmul1p0_" +
+		"zicbom1p0_zicbop1p0_zicboz1p0_zicond1p0_zawrs1p0_zmmul1p0_" +
 		"zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_" +
 		"zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0"
 	b := buildRISCVAttributes(exts)
diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go
index f96c307..489df06 100644
--- a/riscv64/riscv64asm/tables.go
+++ b/riscv64/riscv64asm/tables.go
@@ -1025,6 +1025,8 @@
 	VZEXT_VF2
 	VZEXT_VF4
 	VZEXT_VF8
+	WRS_NTO
+	WRS_STO
 	XNOR
 	XOR
 	XORI
@@ -2049,6 +2051,8 @@
 	VZEXT_VF2:         "VZEXT.VF2",
 	VZEXT_VF4:         "VZEXT.VF4",
 	VZEXT_VF8:         "VZEXT.VF8",
+	WRS_NTO:           "WRS.NTO",
+	WRS_STO:           "WRS.STO",
 	XNOR:              "XNOR",
 	XOR:               "XOR",
 	XORI:              "XORI",
@@ -4090,6 +4094,10 @@
 	{mask: 0xfc0ff07f, value: 0x48022057, op: VZEXT_VF4, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
 	// VZEXT.VF8 vm, vs2, vd
 	{mask: 0xfc0ff07f, value: 0x48012057, op: VZEXT_VF8, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
+	// WRS.NTO
+	{mask: 0xffffffff, value: 0x00d00073, op: WRS_NTO, args: argTypeList{}},
+	// WRS.STO
+	{mask: 0xffffffff, value: 0x01d00073, op: WRS_STO, args: argTypeList{}},
 	// XNOR rd, rs1, rs2
 	{mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
 	// XOR rd, rs1, rs2
diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt
index db1fc8f..f6b4f06 100644
--- a/riscv64/riscv64asm/testdata/gnucases.txt
+++ b/riscv64/riscv64asm/testdata/gnucases.txt
@@ -413,6 +413,10 @@
 # 10.1: "Zihintpause" Extension for Pause Hint, Version 1.0.0
 0f000001|	pause
 
+# "Zawrs" Extension for Wait-on-Reservation-Set Instructions, Version 1.01
+7300d000|	wrs.nto
+7300d001|	wrs.sto
+
 # 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
 b353530e|	czero.eqz x7,x6,x5
 b373530e|	czero.nez x7,x6,x5
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt
index a361d65..ed65915 100644
--- a/riscv64/riscv64asm/testdata/plan9cases.txt
+++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -366,6 +366,10 @@
 # 10.1: "Zihintpause" Extension for Pause Hint, Version 1.0.0
 0f000001|	PAUSE
 
+# "Zawrs" Extension for Wait-on-Reservation-Set Instructions, Version 1.01
+7300d000|	WRSNTO
+7300d001|	WRSSTO
+
 # 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
 b353530e|	CZEROEQZ X5, X6, X7
 b373530e|	CZERONEZ X5, X6, X7
diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go
index 887dd14..605d99f 100644
--- a/riscv64/riscv64spec/spec.go
+++ b/riscv64/riscv64spec/spec.go
@@ -41,6 +41,7 @@
 	"rv_zicond",
 	"rv_zicsr",
 	"rv_zifencei",
+	"rv_zawrs",
 	"rv_zvkg",
 	"rv_zvkned",
 	"rv_zvknha",

Change information

Files:

M riscv64/riscv64asm/objdump_test.go
M riscv64/riscv64asm/objdumpext_test.go
M riscv64/riscv64asm/tables.go
M riscv64/riscv64asm/testdata/gnucases.txt
M riscv64/riscv64asm/testdata/plan9cases.txt
M riscv64/riscv64spec/spec.go

Change size: S

Delta: 6 files changed, 23 insertions(+), 1 deletion(-)

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Kinson Nee (Gerrit)

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Aug 9, 2026, 11:10:49 PM (7 hours ago) Aug 9

to goph...@pubsubhelper.golang.org, Cherry Mui, Gopher Robot, golang-co...@googlegroups.com

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Friendly ping. Please let me know if you would like any changes or additional test coverage for this Zawrs disassembly support CL.

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