[go] cmd/internal/obj/arm64: add assembly syntax for the SVE
fannie zhang (Gerrit)
fannie zhang has uploaded this change for review.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 126 insertions(+), 0 deletions(-)
diff --git a/src/cmd/internal/obj/arm64/doc.go b/src/cmd/internal/obj/arm64/doc.go
index 14f0f4c..0da0d1f 100644
--- a/src/cmd/internal/obj/arm64/doc.go
+++ b/src/cmd/internal/obj/arm64/doc.go
@@ -268,5 +268,107 @@
VST1.P V9.S[1], (R16)(R21) <=> st1 {v9.s}[1], [x16], x28
VST1.P [V13.H8, V14.H8, V15.H8], (R3)(R14) <=> st1 {v13.8h-v15.8h}, [x3], x14
VST1.P [V14.D1, V15.D1], (R7)(R23) <=> st1 {v14.1d, v15.1d}, [x7], x23
+
+The following mapping rules are specific to the SVE instructions.
+
+
+Mnemonics mapping rules
+
+1. If one of the operands is scalable vector register "Zn", add a "Z" prefix to opcode.
+
+ Examples:
+ ZANDVB <Zn>.<T>, <Pg>, <Vd> <=> andv <Bd>, <Pg>, <Zn>.<T>
+ ZANDVS <Zn>.<T>, <Pg>, <Vd> <=> andv <Sd>, <Pg>, <Zn>.<T>
+ ZCLASTAW <Zm>.<T>, <Rdn>, <Pg>, <Rdn> <=> clasta <Wdn>, <Pg>, <Wdn>, <Zm>.<T>
+ ZREV <Zn>.<T>, <Zd>.<T> <=> rev <Zd>.<T>, <Zn>.<T>
+
+2. If the operands only contain basic registers and scalable predicate registers "Pn" or only contain scalable
+predicate registers "Pn", add a "P" prefix to opcode.
+
+ Examples:
+ PDECP <Pg>.<T>, <Rdn> <=> decp <Xdn>, <Pg>.<T>
+ PBICS <Pm>.B, <Pn>.B, <Pg>/Z, <Pd>.B <=> bics <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+ PREV <Pn>.<T>, <Pd>.<T> <=> rev <Pd>.<T>, <Pn>.<T>
+
+3. Name the opcode of "Load/Store vector register" instruction as "ZMOV", and name the opcode of
+"Load/Store predicate register" instruction as "PMOV".
+
+ Example:
+ ZMOV <Zt>, (VL*imm)(Rn|RSP) <=> str <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
+ PMOV (VL*imm)(Rn|RSP), <Pt> <=> ldr <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]
+
+4. Special Cases.
+
+(1). For WHILELE, WHILELO, WHILELS and WHILELT instructions, only the width of the basic register is
+added as the suffix of the opcode.
+
+ Examples:
+ WHILELE <Rm>, <Rn>, <Pd>.<T> <=> whilele <Pd>.<T>, <Xn>, <Xm>
+ WHILELO <Rm>, <Rn>, <Pd>.<T> <=> whilelo <Pd>.<T>, <Xn>, <Xm>
+ WHILELSW <Rm>, <Rn>, <Pd>.<T> <=> whilels <Pd>.<T>, <Wn>, <Wm>
+ WHILELTW <Rm>, <Rn>, <Pd>.<T> <=> whilelt <Pd>.<T>, <Wn>, <Wm>
+
+(2). For instructions like PTRUE, PFALSE and PNEXT, whose opcodes start with "P", keep the opcode unchanged.
+
+ Examples:
+ PTEST <Pn>.B, <Pg> <=> ptest <Pg>, <Pn>.B
+ PFALSE <Pd>.B <=> pfalse <Pd>.B
+
+
+Argument mapping rules
+
+1. Name the zeroing predicate "<Pg>/Z" as "<Pg>.Z", and name the merging predication "<Pg>/M" as "<Pg>.M".
+
+2. Treat the optional pattern specifier "<pattern>" as a separate operand.
+
+ Examples:
+ INCB $<imm>, <pattern>, <Rdn> <=> incb <Xdn>{, <pattern>{, MUL #<imm>}}
+ SQDECB $<imm>, <pattern>, <Rdn>, <Rdn> <=> sqdecb <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
+ UQDECH $<imm>, <pattern>, <Rdn> <=> uqdech <Xdn>{, <pattern>{, MUL #<imm>}}
+ ZUQDECD $<imm>, <pattern>, <Zdn>.D <=> uqdecd <Zdn>.D{, <pattern>{, MUL #<imm>}}
+ PTRUE <pattern>, <Pd>.<T> <=> ptrue <Pd>.<T>{, <pattern>}
+
+ INCB $3, VL4, R1 <=> incb x1, vl4, mul #3
+ ZUQDECD $12, VL1, Z2.D <=> uqdecd z2.d, vl1, mul #12
+ PTRUE VL1, P1.B <=> ptrue p1.b, vl1
+
+3. Addressing mode.
+
+(1). Scalar plus immediate: (VL*imm)(Rn|RSP).
+
+ Examples:
+ ZLD1D (VL*imm)(Rn|RSP), <Pg>.Z, <Zt>.D <=> ld1d { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
+ ZST1W <Zt>.D, <Pg>, (VL*imm)(Rn|RSP) <=> st1w { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
+
+(2). Scalar plus vector, e.g., (<Zm>.D)(Rn|RSP), (<Zm>.S.<mod>)(Rn|RSP), (<Zm>.D<<3)(Rn|RSP) and (<Zm>.D.<mod><<3)(Rn|RSP),
+the "<mod>" can be "UXTW" and "SXTW".
+
+ Examples:
+ ZST1D <Zt>.D, <Pg>, (<Zm>.D<<3)(Rn|RSP) <=> st1d { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
+ ZST1D <Zt>.D, <Pg>, (<Zm>.D.UXTW<<3)(Rn|RSP) <=> st1d { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, uxtw #3]
+ ZLD1B (<Zm.D>.UXTW)(Rn|RSP), <Pg>.Z, <Zt>.D <=> ld1b { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, uxtw]
+ ZLD1B (<Zm.D>)(Rn|RSP), <Pg>.Z, <Zt>.D <=> ld1b { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
+
+(3). Vector plus immediate: imm(<Zn>.D) and imm(<Zn>.S)
+
+ Examples:
+ ZLD1B imm(Zn.S), <Pg>.Z, <Zt>.S <=> ld1b {<Zt>.S}, <Pg>/Z, [<Zn>.S{, #<imm>}]
+ ZST1H <Zt>.D, <Pg>, imm(<Zn>.D) <=> st1h { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
+
+(4). Scalable vector plus scalable vector with extension: (<Zm>.T<<<amount>)(<Zn>.T), (<Zm>.D.SXTW<<<amount>)(<Zn>.D)
+and (<Zm>.D.UXTW<<<amout>)(<Zn>.D).
+
+ Examples:
+ ZADR (Z1.S)(Z2.S), Z3.S <=> adr z3.s, [z2.s, z1.s]
+ ZADR (Z1.S<<2)(Z2.S), Z3.S <=> adr z3.s, [z2.s, z1.s, lsl #2]
+ ZADR (Z1.D<<1)(Z2.D), Z3.D <=> adr z3.d, [z2.d, z1.d, lsl #1]
+ ZADR (Z1.D.UXTW)(Z2.D), Z3.D <=> adr z3.d, [z2.d, z1.d, uxtw]
+ ZADR (Z1.D.SXTW<<1)(Z2.D), Z3.D <=> adr z3.d, [z2.d, z1.d, sxtw #1]
+
+(5). Scalable vector plus scalar: (Rm)(<Zn>.D) and (Rm)(<Zn>.S).
+
+ Examples:
+ ZLDNT1B (Rm)(<Zn>.D), <Pg>.Z, <Zt>.D <=> ldnt1b {<Zt>.D}, <Pg>/Z, [<Zn>.D{, <Xm>}]
+ ZSTNT1H <Zt>.S, <Pg>, (Rm)(<Zn>.S) <=> stnt1h { <Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
*/
package arm64
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fannie zhang (Gerrit)
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1 comment:
Patchset:
Commercial hardware with SVE feature support may be released next year. Considering that users will want to add SVE assembly support for optimization, we hope to predefine the assembly syntax so that users can have clear and consistent patterns. Thank you.
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Cherry Mui (Gerrit)
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6 comments:
Patchset:
The syntax looks okay overall. Thanks.
R=go1.19
File src/cmd/internal/obj/arm64/doc.go:
Patch Set #1, Line 293:
"Load/Store vector register"Remove quotes, just use words. Most of this doc doesn't quote things like this.
Is this literally "VL"? What does it stand for? Maybe it needs an explanation somewhere.
Patch Set #1, Line 322:
<pattern>What is a pattern? What does it look like?
Patch Set #1, Line 335:
3. Addressing mode.Does all the A plus B below mean a memory location at address A+B, or just plainly adding two numbers? The syntax below makes sense if it is a memory location.
In this doc GNU syntax usually use lowercase. Can this be lowercase? Also MUL in a few other places.
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fannie zhang (Gerrit)
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fannie zhang uploaded patch set #2 to this change.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 133 insertions(+), 0 deletions(-)
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fannie zhang (Gerrit)
Attention is currently required from: Keith Randall, Ian Lance Taylor, Cherry Mui.
6 comments:
Patchset:
All done. Thank you for the review.
File src/cmd/internal/obj/arm64/doc.go:
Patch Set #1, Line 293:
"Load/Store vector register"Remove quotes, just use words. Most of this doc doesn't quote things like this.
Done
Is this literally "VL"? What does it stand for? Maybe it needs an explanation somewhere.
When included as part of the assembler syntax for an instruction, MUL VL indicates that the specified immediate index value is multiplied by the size of the addressed vector or predicate in memory, measured in bytes, irrespective of predication.
When used in pseudocode, the symbol VL represents the vector length, measured in bits.
I will add the explanation for it.
Thank you.
Patch Set #1, Line 322:
<pattern>What is a pattern? What does it look like?
Done
Patch Set #1, Line 335:
3. Addressing mode.
Does all the A plus B below mean a memory location at address A+B, or just plainly adding two number […]
All of them mean a memory locationm, but the address is not simply A+B.
For example: scalar plus vector, the instruction "LD1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]"
base = Xn
offset = Zmfor e from 0 to VL/64
addr = base + offset[e*64+64-1:e*64]
result[e*64_64-1:e*64] = load[addr]
Zt = resultThank you.
In this doc GNU syntax usually use lowercase. Can this be lowercase? Also MUL in a few other places.
Done
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Fannie Zhang (Gerrit)
Attention is currently required from: Keith Randall, Ian Lance Taylor, Cherry Mui.
Fannie Zhang uploaded patch set #3 to this change.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 136 insertions(+), 0 deletions(-)
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Fannie Zhang (Gerrit)
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Patch set 4:Trust +1
1 comment:
Patchset:
Could you please help to review this patch? Thank you.
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Fannie Zhang (Gerrit)
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1 comment:
Patchset:
@Cherry, Is it possible for this patch to be merged to go1.19? Thank you.
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Fannie Zhang (Gerrit)
Attention is currently required from: Cherry Mui, Fannie Zhang, Ian Lance Taylor, Keith Randall.
Fannie Zhang uploaded patch set #9 to this change.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 142 insertions(+), 6 deletions(-)
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Fannie Zhang (Gerrit)
Attention is currently required from: Cherry Mui, Fannie Zhang, Ian Lance Taylor, Keith Randall.
Fannie Zhang uploaded patch set #10 to this change.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 129 insertions(+), 2 deletions(-)
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Fannie Zhang (Gerrit)
Attention is currently required from: Cherry Mui, Fannie Zhang, Ian Lance Taylor, Keith Randall.
Fannie Zhang uploaded patch set #11 to this change.
cmd/internal/obj/arm64: add assembly syntax for the SVE
The SVE (Scalable Vector Extension) is a new instruction set,
and some SVE-specific argument types are newly introduced.
But their Go assembly syntax is not defined, so we first add
mapping rules for SVE before implementing them, so that if
users want to add the support in the assembler, there can be
a clear and consistent pattern.
We posted a discussion of SVE assembly syntax to the golang-dev
mailing list (https://groups.google.com/forum/#!topic/golang-dev/sYctj3HrXvc),
this patch uses the recommended format.
SVE related documents can be found on:
1. https://developer.arm.com/tools-and-software/server-and-hpc/compile/arm-instruction-emulator/resources/tutorials/sve
2. https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions?lang=en
Change-Id: I95649dcffc3309722430b6a1ba215aa414f909ac
---
M src/cmd/internal/obj/arm64/doc.go
1 file changed, 140 insertions(+), 1 deletion(-)
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Fannie Zhang (Gerrit)
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Patch set 11:Run-TryBot +1
Fannie Zhang (Gerrit)
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1 comment:
Patchset:
Kindly ping.
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Cherry Mui (Gerrit)
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1 comment:
Patchset:
This CL looks good. But I think we want submit after the assembler adds the support of these instructions. So I don't think we need any action for the moment. Thanks.
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Fannie Zhang (Gerrit)
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1 comment:
Patchset:
This CL looks good. […]
Thank you for the comments.
This patch https://go-review.googlesource.com/c/go/+/153358 is to add the support of these instructions, it is ready for a long time ago. I will deal with the implementation patch first and then act on this patch. Thank you.
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Cherry Mui (Gerrit)
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1 comment:
Patchset:
Thank you for the comments. […]
What is the story between this and CL 424137? I thought the plan is to add new instructions via the new path from CL 424137?
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Fannie Zhang (Gerrit)
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1 comment:
Patchset:
What is the story between this and CL 424137? I thought the plan is to add new instructions via the […]
There is no association between these two patches, the CL 153358 is a very old patch, which is a prototype for SVE instructions.
Adding new instructions via new path is the best way, but we can keep the CL 153358 path as a backup in case someone desperately needs an sve instruction, in case something blocks the implementation of the new path.
So the CL 153358 does not need any action for the time either. Thank you.
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Cherry Mui (Gerrit)
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1 comment:
Patchset:
There is no association between these two patches, the CL 153358 is a very old patch, which is a pro […]
Thanks. Sounds good. Once we have SVE support in the assembler (probably via the new path), we can check in this CL.
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Fannie Zhang (Gerrit)
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Patchset:
Thanks. Sounds good. […]
Okay, thanks.
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