[go/dev.simd] [dev.simd] simd, cmd/compile: change RoundToEven to Round
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Junyang Shao (Gerrit)
4:48 PM (6 hours ago) 4:48 PM
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Junyang Shao has uploaded the change for review![]( "Open in Gerrit")
Commit message
[dev.simd] simd, cmd/compile: change RoundToEven to Round
For #78979.
Change-Id: I7116fa731a18e201c5fc12874657f6d6ee38b374
Change diff
diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
index 620fe56..8fdf860 100644
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
@@ -833,22 +833,22 @@
(RotateRightUint64x2 ...) => (VPRORVQ128 ...)
(RotateRightUint64x4 ...) => (VPRORVQ256 ...)
(RotateRightUint64x8 ...) => (VPRORVQ512 ...)
-(RoundToEvenFloat32x4 x) => (VROUNDPS128 [0] x)
-(RoundToEvenFloat32x8 x) => (VROUNDPS256 [0] x)
-(RoundToEvenFloat64x2 x) => (VROUNDPD128 [0] x)
-(RoundToEvenFloat64x4 x) => (VROUNDPD256 [0] x)
-(RoundToEvenScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x)
-(RoundToEvenScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x)
-(RoundToEvenScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x)
-(RoundToEvenScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x)
-(RoundToEvenScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x)
-(RoundToEvenScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x)
-(RoundToEvenScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x)
-(RoundToEvenScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x)
-(RoundToEvenScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x)
-(RoundToEvenScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x)
-(RoundToEvenScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x)
-(RoundToEvenScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x)
+(RoundFloat32x4 x) => (VROUNDPS128 [0] x)
+(RoundFloat32x8 x) => (VROUNDPS256 [0] x)
+(RoundFloat64x2 x) => (VROUNDPD128 [0] x)
+(RoundFloat64x4 x) => (VROUNDPD256 [0] x)
+(RoundScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x)
+(RoundScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x)
+(RoundScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x)
+(RoundScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x)
+(RoundScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x)
+(RoundScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x)
+(RoundScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x)
+(RoundScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x)
+(RoundScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x)
+(RoundScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x)
+(RoundScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x)
+(RoundScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x)
(SHA1FourRoundsUint32x4 ...) => (SHA1RNDS4128 ...)
(SHA1Message1Uint32x4 ...) => (SHA1MSG1128 ...)
(SHA1Message2Uint32x4 ...) => (SHA1MSG2128 ...)
diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
index 99aa9e2..f1d87ab 100644
--- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
@@ -769,10 +769,10 @@
{name: "RotateRightUint64x2", argLength: 2}, // ARCH:amd64
{name: "RotateRightUint64x4", argLength: 2}, // ARCH:amd64
{name: "RotateRightUint64x8", argLength: 2}, // ARCH:amd64
- {name: "RoundToEvenFloat32x4", argLength: 1}, // ARCH:amd64
- {name: "RoundToEvenFloat32x8", argLength: 1}, // ARCH:amd64
- {name: "RoundToEvenFloat64x2", argLength: 1}, // ARCH:amd64
- {name: "RoundToEvenFloat64x4", argLength: 1}, // ARCH:amd64
+ {name: "RoundFloat32x4", argLength: 1}, // ARCH:amd64
+ {name: "RoundFloat32x8", argLength: 1}, // ARCH:amd64
+ {name: "RoundFloat64x2", argLength: 1}, // ARCH:amd64
+ {name: "RoundFloat64x4", argLength: 1}, // ARCH:amd64
{name: "SHA1Message1Uint32x4", argLength: 2}, // ARCH:amd64
{name: "SHA1Message2Uint32x4", argLength: 2}, // ARCH:amd64
{name: "SHA1NextEUint32x4", argLength: 2}, // ARCH:amd64
@@ -1238,18 +1238,18 @@
{name: "RotateAllRightUint64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64
{name: "RotateAllRightUint64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
{name: "RotateAllRightUint64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
- {name: "RoundToEvenScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat32x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat32x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat32x16", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat64x2", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat64x4", argLength: 1, aux: "UInt8"}, // ARCH:amd64
+ {name: "RoundScaledResidueFloat64x8", argLength: 1, aux: "UInt8"}, // ARCH:amd64
{name: "SHA1FourRoundsUint32x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64
{name: "Select128FromPairFloat32x8", argLength: 2, aux: "UInt8"}, // ARCH:amd64
{name: "Select128FromPairFloat64x4", argLength: 2, aux: "UInt8"}, // ARCH:amd64
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index dd65c70..acb2d81 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -6950,10 +6950,10 @@
OpRotateRightUint64x2
OpRotateRightUint64x4
OpRotateRightUint64x8
- OpRoundToEvenFloat32x4
- OpRoundToEvenFloat32x8
- OpRoundToEvenFloat64x2
- OpRoundToEvenFloat64x4
+ OpRoundFloat32x4
+ OpRoundFloat32x8
+ OpRoundFloat64x2
+ OpRoundFloat64x4
OpSHA1Message1Uint32x4
OpSHA1Message2Uint32x4
OpSHA1NextEUint32x4
@@ -7419,18 +7419,18 @@
OpRotateAllRightUint64x2
OpRotateAllRightUint64x4
OpRotateAllRightUint64x8
- OpRoundToEvenScaledFloat32x4
- OpRoundToEvenScaledFloat32x8
- OpRoundToEvenScaledFloat32x16
- OpRoundToEvenScaledFloat64x2
- OpRoundToEvenScaledFloat64x4
- OpRoundToEvenScaledFloat64x8
- OpRoundToEvenScaledResidueFloat32x4
- OpRoundToEvenScaledResidueFloat32x8
- OpRoundToEvenScaledResidueFloat32x16
- OpRoundToEvenScaledResidueFloat64x2
- OpRoundToEvenScaledResidueFloat64x4
- OpRoundToEvenScaledResidueFloat64x8
+ OpRoundScaledFloat32x4
+ OpRoundScaledFloat32x8
+ OpRoundScaledFloat32x16
+ OpRoundScaledFloat64x2
+ OpRoundScaledFloat64x4
+ OpRoundScaledFloat64x8
+ OpRoundScaledResidueFloat32x4
+ OpRoundScaledResidueFloat32x8
+ OpRoundScaledResidueFloat32x16
+ OpRoundScaledResidueFloat64x2
+ OpRoundScaledResidueFloat64x4
+ OpRoundScaledResidueFloat64x8
OpSHA1FourRoundsUint32x4
OpSelect128FromPairFloat32x8
OpSelect128FromPairFloat64x4
@@ -93324,22 +93324,22 @@
generic: true,
},
{
- name: "RoundToEvenFloat32x4",
+ name: "RoundFloat32x4",
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenFloat32x8",
+ name: "RoundFloat32x8",
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenFloat64x2",
+ name: "RoundFloat64x2",
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenFloat64x4",
+ name: "RoundFloat64x4",
argLen: 1,
generic: true,
},
@@ -95761,73 +95761,73 @@
generic: true,
},
{
- name: "RoundToEvenScaledFloat32x4",
+ name: "RoundScaledFloat32x4",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledFloat32x8",
+ name: "RoundScaledFloat32x8",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledFloat32x16",
+ name: "RoundScaledFloat32x16",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledFloat64x2",
+ name: "RoundScaledFloat64x2",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledFloat64x4",
+ name: "RoundScaledFloat64x4",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledFloat64x8",
+ name: "RoundScaledFloat64x8",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat32x4",
+ name: "RoundScaledResidueFloat32x4",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat32x8",
+ name: "RoundScaledResidueFloat32x8",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat32x16",
+ name: "RoundScaledResidueFloat32x16",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat64x2",
+ name: "RoundScaledResidueFloat64x2",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat64x4",
+ name: "RoundScaledResidueFloat64x4",
auxType: auxUInt8,
argLen: 1,
generic: true,
},
{
- name: "RoundToEvenScaledResidueFloat64x8",
+ name: "RoundScaledResidueFloat64x8",
auxType: auxUInt8,
argLen: 1,
generic: true,
diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index d034ba8..c2c09cc 100644
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -4881,40 +4881,40 @@
case OpRound64F:
v.Op = OpAMD64LoweredRound64F
return true
+ case OpRoundFloat32x4:
+ return rewriteValueAMD64_OpRoundFloat32x4(v)
+ case OpRoundFloat32x8:
+ return rewriteValueAMD64_OpRoundFloat32x8(v)
+ case OpRoundFloat64x2:
+ return rewriteValueAMD64_OpRoundFloat64x2(v)
+ case OpRoundFloat64x4:
+ return rewriteValueAMD64_OpRoundFloat64x4(v)
+ case OpRoundScaledFloat32x16:
+ return rewriteValueAMD64_OpRoundScaledFloat32x16(v)
+ case OpRoundScaledFloat32x4:
+ return rewriteValueAMD64_OpRoundScaledFloat32x4(v)
+ case OpRoundScaledFloat32x8:
+ return rewriteValueAMD64_OpRoundScaledFloat32x8(v)
+ case OpRoundScaledFloat64x2:
+ return rewriteValueAMD64_OpRoundScaledFloat64x2(v)
+ case OpRoundScaledFloat64x4:
+ return rewriteValueAMD64_OpRoundScaledFloat64x4(v)
+ case OpRoundScaledFloat64x8:
+ return rewriteValueAMD64_OpRoundScaledFloat64x8(v)
+ case OpRoundScaledResidueFloat32x16:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat32x16(v)
+ case OpRoundScaledResidueFloat32x4:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat32x4(v)
+ case OpRoundScaledResidueFloat32x8:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat32x8(v)
+ case OpRoundScaledResidueFloat64x2:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat64x2(v)
+ case OpRoundScaledResidueFloat64x4:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat64x4(v)
+ case OpRoundScaledResidueFloat64x8:
+ return rewriteValueAMD64_OpRoundScaledResidueFloat64x8(v)
case OpRoundToEven:
return rewriteValueAMD64_OpRoundToEven(v)
- case OpRoundToEvenFloat32x4:
- return rewriteValueAMD64_OpRoundToEvenFloat32x4(v)
- case OpRoundToEvenFloat32x8:
- return rewriteValueAMD64_OpRoundToEvenFloat32x8(v)
- case OpRoundToEvenFloat64x2:
- return rewriteValueAMD64_OpRoundToEvenFloat64x2(v)
- case OpRoundToEvenFloat64x4:
- return rewriteValueAMD64_OpRoundToEvenFloat64x4(v)
- case OpRoundToEvenScaledFloat32x16:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat32x16(v)
- case OpRoundToEvenScaledFloat32x4:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat32x4(v)
- case OpRoundToEvenScaledFloat32x8:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat32x8(v)
- case OpRoundToEvenScaledFloat64x2:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat64x2(v)
- case OpRoundToEvenScaledFloat64x4:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat64x4(v)
- case OpRoundToEvenScaledFloat64x8:
- return rewriteValueAMD64_OpRoundToEvenScaledFloat64x8(v)
- case OpRoundToEvenScaledResidueFloat32x16:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x16(v)
- case OpRoundToEvenScaledResidueFloat32x4:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x4(v)
- case OpRoundToEvenScaledResidueFloat32x8:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x8(v)
- case OpRoundToEvenScaledResidueFloat64x2:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x2(v)
- case OpRoundToEvenScaledResidueFloat64x4:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x4(v)
- case OpRoundToEvenScaledResidueFloat64x8:
- return rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x8(v)
case OpRsh16Ux16:
return rewriteValueAMD64_OpRsh16Ux16(v)
case OpRsh16Ux32:
@@ -75491,21 +75491,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEven(v *Value) bool {
+func rewriteValueAMD64_OpRoundFloat32x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEven x)
- // result: (ROUNDSD [0] x)
- for {
- x := v_0
- v.reset(OpAMD64ROUNDSD)
- v.AuxInt = int8ToAuxInt(0)
- v.AddArg(x)
- return true
- }
-}
-func rewriteValueAMD64_OpRoundToEvenFloat32x4(v *Value) bool {
- v_0 := v.Args[0]
- // match: (RoundToEvenFloat32x4 x)
+ // match: (RoundFloat32x4 x)
// result: (VROUNDPS128 [0] x)
for {
x := v_0
@@ -75515,9 +75503,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenFloat32x8(v *Value) bool {
+func rewriteValueAMD64_OpRoundFloat32x8(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenFloat32x8 x)
+ // match: (RoundFloat32x8 x)
// result: (VROUNDPS256 [0] x)
for {
x := v_0
@@ -75527,9 +75515,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenFloat64x2(v *Value) bool {
+func rewriteValueAMD64_OpRoundFloat64x2(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenFloat64x2 x)
+ // match: (RoundFloat64x2 x)
// result: (VROUNDPD128 [0] x)
for {
x := v_0
@@ -75539,9 +75527,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenFloat64x4(v *Value) bool {
+func rewriteValueAMD64_OpRoundFloat64x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenFloat64x4 x)
+ // match: (RoundFloat64x4 x)
// result: (VROUNDPD256 [0] x)
for {
x := v_0
@@ -75551,9 +75539,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat32x16(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat32x16(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat32x16 [a] x)
+ // match: (RoundScaledFloat32x16 [a] x)
// result: (VRNDSCALEPS512 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75564,9 +75552,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat32x4(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat32x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat32x4 [a] x)
+ // match: (RoundScaledFloat32x4 [a] x)
// result: (VRNDSCALEPS128 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75577,9 +75565,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat32x8(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat32x8(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat32x8 [a] x)
+ // match: (RoundScaledFloat32x8 [a] x)
// result: (VRNDSCALEPS256 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75590,9 +75578,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat64x2(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat64x2(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat64x2 [a] x)
+ // match: (RoundScaledFloat64x2 [a] x)
// result: (VRNDSCALEPD128 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75603,9 +75591,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat64x4(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat64x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat64x4 [a] x)
+ // match: (RoundScaledFloat64x4 [a] x)
// result: (VRNDSCALEPD256 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75616,9 +75604,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledFloat64x8(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledFloat64x8(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledFloat64x8 [a] x)
+ // match: (RoundScaledFloat64x8 [a] x)
// result: (VRNDSCALEPD512 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75629,9 +75617,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x16(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat32x16(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat32x16 [a] x)
+ // match: (RoundScaledResidueFloat32x16 [a] x)
// result: (VREDUCEPS512 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75642,9 +75630,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x4(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat32x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat32x4 [a] x)
+ // match: (RoundScaledResidueFloat32x4 [a] x)
// result: (VREDUCEPS128 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75655,9 +75643,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat32x8(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat32x8(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat32x8 [a] x)
+ // match: (RoundScaledResidueFloat32x8 [a] x)
// result: (VREDUCEPS256 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75668,9 +75656,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x2(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat64x2(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat64x2 [a] x)
+ // match: (RoundScaledResidueFloat64x2 [a] x)
// result: (VREDUCEPD128 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75681,9 +75669,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x4(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat64x4(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat64x4 [a] x)
+ // match: (RoundScaledResidueFloat64x4 [a] x)
// result: (VREDUCEPD256 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75694,9 +75682,9 @@
return true
}
}
-func rewriteValueAMD64_OpRoundToEvenScaledResidueFloat64x8(v *Value) bool {
+func rewriteValueAMD64_OpRoundScaledResidueFloat64x8(v *Value) bool {
v_0 := v.Args[0]
- // match: (RoundToEvenScaledResidueFloat64x8 [a] x)
+ // match: (RoundScaledResidueFloat64x8 [a] x)
// result: (VREDUCEPD512 [a+0] x)
for {
a := auxIntToUint8(v.AuxInt)
@@ -75707,6 +75695,18 @@
return true
}
}
+func rewriteValueAMD64_OpRoundToEven(v *Value) bool {
+ v_0 := v.Args[0]
+ // match: (RoundToEven x)
+ // result: (ROUNDSD [0] x)
+ for {
+ x := v_0
+ v.reset(OpAMD64ROUNDSD)
+ v.AuxInt = int8ToAuxInt(0)
+ v.AddArg(x)
+ return true
+ }
+}
func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool {
v_1 := v.Args[1]
v_0 := v.Args[0]
diff --git a/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
index cebed2e..e790254 100644
--- a/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
+++ b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
@@ -843,22 +843,22 @@
addF(simdPackage, "Uint64x2.RotateRight", opLen2(ssa.OpRotateRightUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.RotateRight", opLen2(ssa.OpRotateRightUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.RotateRight", opLen2(ssa.OpRotateRightUint64x8, types.TypeVec512), sys.AMD64)
- addF(simdPackage, "Float32x4.RoundToEven", opLen1(ssa.OpRoundToEvenFloat32x4, types.TypeVec128), sys.AMD64)
- addF(simdPackage, "Float32x8.RoundToEven", opLen1(ssa.OpRoundToEvenFloat32x8, types.TypeVec256), sys.AMD64)
- addF(simdPackage, "Float64x2.RoundToEven", opLen1(ssa.OpRoundToEvenFloat64x2, types.TypeVec128), sys.AMD64)
- addF(simdPackage, "Float64x4.RoundToEven", opLen1(ssa.OpRoundToEvenFloat64x4, types.TypeVec256), sys.AMD64)
- addF(simdPackage, "Float32x4.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat32x4, types.TypeVec128, 4), sys.AMD64)
- addF(simdPackage, "Float32x8.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat32x8, types.TypeVec256, 4), sys.AMD64)
- addF(simdPackage, "Float32x16.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat32x16, types.TypeVec512, 4), sys.AMD64)
- addF(simdPackage, "Float64x2.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat64x2, types.TypeVec128, 4), sys.AMD64)
- addF(simdPackage, "Float64x4.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat64x4, types.TypeVec256, 4), sys.AMD64)
- addF(simdPackage, "Float64x8.RoundToEvenScaled", opLen1Imm8(ssa.OpRoundToEvenScaledFloat64x8, types.TypeVec512, 4), sys.AMD64)
- addF(simdPackage, "Float32x4.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64)
- addF(simdPackage, "Float32x8.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64)
- addF(simdPackage, "Float32x16.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64)
- addF(simdPackage, "Float64x2.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64)
- addF(simdPackage, "Float64x4.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64)
- addF(simdPackage, "Float64x8.RoundToEvenScaledResidue", opLen1Imm8(ssa.OpRoundToEvenScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64)
+ addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
+ addF(simdPackage, "Float64x4.Round", opLen1(ssa.OpRoundFloat64x4, types.TypeVec256), sys.AMD64)
+ addF(simdPackage, "Float32x4.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x4, types.TypeVec128, 4), sys.AMD64)
+ addF(simdPackage, "Float32x8.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x8, types.TypeVec256, 4), sys.AMD64)
+ addF(simdPackage, "Float32x16.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat32x16, types.TypeVec512, 4), sys.AMD64)
+ addF(simdPackage, "Float64x2.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x2, types.TypeVec128, 4), sys.AMD64)
+ addF(simdPackage, "Float64x4.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x4, types.TypeVec256, 4), sys.AMD64)
+ addF(simdPackage, "Float64x8.RoundScaled", opLen1Imm8(ssa.OpRoundScaledFloat64x8, types.TypeVec512, 4), sys.AMD64)
+ addF(simdPackage, "Float32x4.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x4, types.TypeVec128, 4), sys.AMD64)
+ addF(simdPackage, "Float32x8.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x8, types.TypeVec256, 4), sys.AMD64)
+ addF(simdPackage, "Float32x16.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat32x16, types.TypeVec512, 4), sys.AMD64)
+ addF(simdPackage, "Float64x2.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x2, types.TypeVec128, 4), sys.AMD64)
+ addF(simdPackage, "Float64x4.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x4, types.TypeVec256, 4), sys.AMD64)
+ addF(simdPackage, "Float64x8.RoundScaledResidue", opLen1Imm8(ssa.OpRoundScaledResidueFloat64x8, types.TypeVec512, 4), sys.AMD64)
addF(simdPackage, "Uint32x4.SHA1FourRounds", opLen2Imm8_SHA1RNDS4(ssa.OpSHA1FourRoundsUint32x4, types.TypeVec128, 0), sys.AMD64)
addF(simdPackage, "Uint32x4.SHA1Message1", opLen2(ssa.OpSHA1Message1Uint32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint32x4.SHA1Message2", opLen2(ssa.OpSHA1Message2Uint32x4, types.TypeVec128), sys.AMD64)
diff --git a/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/categories.yaml b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/categories.yaml
index 77f87da..5db68a6 100644
--- a/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/categories.yaml
+++ b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/categories.yaml
@@ -20,17 +20,17 @@
documentation: !string |-
// NAME multiplies each element of x by 2 raised to the power of the
// floor of the corresponding element in y.
-- go: RoundToEven
+- go: Round
commutative: false
constImm: 0
documentation: !string |-
// NAME rounds elements to the nearest integer, rounding ties to even.
-- go: RoundToEvenScaled
+- go: RoundScaled
commutative: false
constImm: 0
documentation: !string |-
// NAME rounds elements with specified precision.
-- go: RoundToEvenScaledResidue
+- go: RoundScaledResidue
commutative: false
constImm: 0
documentation: !string |-
diff --git a/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go.yaml b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go.yaml
index 303647b..72eea9d 100644
--- a/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go.yaml
+++ b/src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go.yaml
@@ -26,7 +26,7 @@
in: *2fp
out: *1fp
-- go: "RoundToEven|Ceil|Floor|Trunc"
+- go: "Round|Ceil|Floor|Trunc"
regexpTag: "fp"
asm: "VROUNDP[SD]"
in:
@@ -35,7 +35,7 @@
const: 0 # place holder
out: *1fp
-- go: "(RoundToEven|Ceil|Floor|Trunc)Scaled"
+- go: "(Round|Ceil|Floor|Trunc)Scaled"
regexpTag: "fp"
asm: "VRNDSCALEP[SD]"
in:
@@ -45,7 +45,7 @@
immOffset: 4 # "M", round to numbers with M digits after dot(by means of binary number).
name: prec
out: *1fp
-- go: "(RoundToEven|Ceil|Floor|Trunc)ScaledResidue"
+- go: "(Round|Ceil|Floor|Trunc)ScaledResidue"
regexpTag: "fp"
asm: "VREDUCEP[SD]"
in:
diff --git a/src/simd/archsimd/internal/simd_test/simulation_helpers_test.go b/src/simd/archsimd/internal/simd_test/simulation_helpers_test.go
index ac60b6d..0a6447f 100644
--- a/src/simd/archsimd/internal/simd_test/simulation_helpers_test.go
+++ b/src/simd/archsimd/internal/simd_test/simulation_helpers_test.go
@@ -54,7 +54,7 @@
return ^x
}
func round[T float](x T) T {
- return T(math.RoundToEven(float64(x)))
+ return T(math.Round(float64(x)))
}
func sqrt[T float](x T) T {
return T(math.Sqrt(float64(x)))
diff --git a/src/simd/archsimd/internal/simd_test/unary_test.go b/src/simd/archsimd/internal/simd_test/unary_test.go
index 097feb6..3faf566 100644
--- a/src/simd/archsimd/internal/simd_test/unary_test.go
+++ b/src/simd/archsimd/internal/simd_test/unary_test.go
@@ -46,10 +46,10 @@
}
func TestRound(t *testing.T) {
- testFloat32x4Unary(t, archsimd.Float32x4.RoundToEven, roundSlice[float32])
- testFloat32x8Unary(t, archsimd.Float32x8.RoundToEven, roundSlice[float32])
- testFloat64x2Unary(t, archsimd.Float64x2.RoundToEven, roundSlice[float64])
- testFloat64x4Unary(t, archsimd.Float64x4.RoundToEven, roundSlice[float64])
+ testFloat32x4Unary(t, archsimd.Float32x4.Round, roundSlice[float32])
+ testFloat32x8Unary(t, archsimd.Float32x8.Round, roundSlice[float32])
+ testFloat64x2Unary(t, archsimd.Float64x2.Round, roundSlice[float64])
+ testFloat64x4Unary(t, archsimd.Float64x4.Round, roundSlice[float64])
if archsimd.X86.AVX512() {
// testFloat32x16Unary(t, archsimd.Float32x16.Round, roundSlice[float32]) // missing
// testFloat64x8Unary(t, archsimd.Float64x8.Round, roundSlice[float64]) // missing
diff --git a/src/simd/archsimd/ops_amd64.go b/src/simd/archsimd/ops_amd64.go
index 2e61806..b105206 100644
--- a/src/simd/archsimd/ops_amd64.go
+++ b/src/simd/archsimd/ops_amd64.go
@@ -4936,115 +4936,115 @@
// Asm: VPRORVQ, CPU Feature: AVX512
func (x Uint64x8) RotateRight(y Uint64x8) Uint64x8
-/* RoundToEven */
+/* Round */
-// RoundToEven rounds elements to the nearest integer, rounding ties to even.
+// Round rounds elements to the nearest integer, rounding ties to even.
//
// Asm: VROUNDPS, CPU Feature: AVX
-func (x Float32x4) RoundToEven() Float32x4
+func (x Float32x4) Round() Float32x4
-// RoundToEven rounds elements to the nearest integer, rounding ties to even.
+// Round rounds elements to the nearest integer, rounding ties to even.
//
// Asm: VROUNDPS, CPU Feature: AVX
-func (x Float32x8) RoundToEven() Float32x8
+func (x Float32x8) Round() Float32x8
-// RoundToEven rounds elements to the nearest integer, rounding ties to even.
+// Round rounds elements to the nearest integer, rounding ties to even.
//
// Asm: VROUNDPD, CPU Feature: AVX
-func (x Float64x2) RoundToEven() Float64x2
+func (x Float64x2) Round() Float64x2
-// RoundToEven rounds elements to the nearest integer, rounding ties to even.
+// Round rounds elements to the nearest integer, rounding ties to even.
//
// Asm: VROUNDPD, CPU Feature: AVX
-func (x Float64x4) RoundToEven() Float64x4
+func (x Float64x4) Round() Float64x4
-/* RoundToEvenScaled */
+/* RoundScaled */
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPS, CPU Feature: AVX512
-func (x Float32x4) RoundToEvenScaled(prec uint8) Float32x4
+func (x Float32x4) RoundScaled(prec uint8) Float32x4
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPS, CPU Feature: AVX512
-func (x Float32x8) RoundToEvenScaled(prec uint8) Float32x8
+func (x Float32x8) RoundScaled(prec uint8) Float32x8
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPS, CPU Feature: AVX512
-func (x Float32x16) RoundToEvenScaled(prec uint8) Float32x16
+func (x Float32x16) RoundScaled(prec uint8) Float32x16
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPD, CPU Feature: AVX512
-func (x Float64x2) RoundToEvenScaled(prec uint8) Float64x2
+func (x Float64x2) RoundScaled(prec uint8) Float64x2
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPD, CPU Feature: AVX512
-func (x Float64x4) RoundToEvenScaled(prec uint8) Float64x4
+func (x Float64x4) RoundScaled(prec uint8) Float64x4
-// RoundToEvenScaled rounds elements with specified precision.
+// RoundScaled rounds elements with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VRNDSCALEPD, CPU Feature: AVX512
-func (x Float64x8) RoundToEvenScaled(prec uint8) Float64x8
+func (x Float64x8) RoundScaled(prec uint8) Float64x8
-/* RoundToEvenScaledResidue */
+/* RoundScaledResidue */
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPS, CPU Feature: AVX512
-func (x Float32x4) RoundToEvenScaledResidue(prec uint8) Float32x4
+func (x Float32x4) RoundScaledResidue(prec uint8) Float32x4
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPS, CPU Feature: AVX512
-func (x Float32x8) RoundToEvenScaledResidue(prec uint8) Float32x8
+func (x Float32x8) RoundScaledResidue(prec uint8) Float32x8
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPS, CPU Feature: AVX512
-func (x Float32x16) RoundToEvenScaledResidue(prec uint8) Float32x16
+func (x Float32x16) RoundScaledResidue(prec uint8) Float32x16
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPD, CPU Feature: AVX512
-func (x Float64x2) RoundToEvenScaledResidue(prec uint8) Float64x2
+func (x Float64x2) RoundScaledResidue(prec uint8) Float64x2
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPD, CPU Feature: AVX512
-func (x Float64x4) RoundToEvenScaledResidue(prec uint8) Float64x4
+func (x Float64x4) RoundScaledResidue(prec uint8) Float64x4
-// RoundToEvenScaledResidue computes the difference after rounding with specified precision.
+// RoundScaledResidue computes the difference after rounding with specified precision.
//
// A non-constant value of prec may result in significantly worse performance for this operation.
//
// Asm: VREDUCEPD, CPU Feature: AVX512
-func (x Float64x8) RoundToEvenScaledResidue(prec uint8) Float64x8
+func (x Float64x8) RoundScaledResidue(prec uint8) Float64x8
/* SHA1FourRounds */
Change information
Files:
- M src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
- M src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
- M src/cmd/compile/internal/ssa/opGen.go
- M src/cmd/compile/internal/ssa/rewriteAMD64.go
- M src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
- M src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/categories.yaml
- M src/simd/archsimd/_gen/simdgen/ops/FPonlyArith/go.yaml
- M src/simd/archsimd/internal/simd_test/simulation_helpers_test.go
- M src/simd/archsimd/internal/simd_test/unary_test.go
- M src/simd/archsimd/ops_amd64.go
Change size: L
Delta: 10 files changed, 202 insertions(+), 202 deletions(-)
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Junyang Shao uploaded new patchset![]( "Open in Gerrit")
Junyang Shao uploaded patch set #2 to this change.
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| Commit-Queue | +1 |
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