[go] cmd/compile: cleanup PPC64 atomics ssa asm generation

[Jorropo (Gerrit)]

Jorropo has uploaded the change for review

Commit message

cmd/compile: cleanup PPC64 atomics ssa asm generation

Follows up CL 774020.

This should have no behavior change.

Change-Id: I5f1070bc5740c477654de10393d9c498ce257728

Change diff

diff --git a/src/cmd/compile/internal/ppc64/ssa.go b/src/cmd/compile/internal/ppc64/ssa.go
index a0d81d3..316d18d 100644
--- a/src/cmd/compile/internal/ppc64/ssa.go
+++ b/src/cmd/compile/internal/ppc64/ssa.go
@@ -146,8 +146,7 @@
 		r1 := v.Args[1].Reg()
 		// LWSYNC - Assuming shared data not write-through-required nor
 		// caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b.
-		plwsync := s.Prog(ppc64.ALWSYNC)
-		plwsync.To.Type = obj.TYPE_NONE
+		s.Prog(ppc64.ALWSYNC)
 		// LBAR or LWAR
 		p := s.Prog(ld)
 		p.From.Type = obj.TYPE_MEM
@@ -194,9 +193,8 @@
 		r0 := v.Args[0].Reg()
 		r1 := v.Args[1].Reg()
 		out := v.Reg0()
-		// LWSYNC - Provide acquire ordering to pair with the
-		// release (pre-LWSYNC) above, making the operation
-		// sequentially consistent.
+		// LWSYNC - Assuming shared data not write-through-required nor
+		// caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b.
 		s.Prog(ppc64.ALWSYNC)
 		// LDAR or LWAR
 		p := s.Prog(ld)
@@ -232,8 +230,7 @@
 		// LWSYNC - Provide acquire ordering to pair with the
 		// release (pre-LWSYNC) above, making the operation
 		// sequentially consistent.
-		plwsync2 := s.Prog(ppc64.ALWSYNC)
-		plwsync2.To.Type = obj.TYPE_NONE
+		s.Prog(ppc64.ALWSYNC)
 
 	case ssa.OpPPC64LoweredAtomicExchange8,
 		ssa.OpPPC64LoweredAtomicExchange32,
@@ -258,8 +255,7 @@
 		out := v.Reg0()
 		// LWSYNC - Assuming shared data not write-through-required nor
 		// caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b.
-		plwsync := s.Prog(ppc64.ALWSYNC)
-		plwsync.To.Type = obj.TYPE_NONE
+		s.Prog(ppc64.ALWSYNC)
 		// L[B|W|D]AR
 		p := s.Prog(ld)
 		p.From.Type = obj.TYPE_MEM
@@ -277,8 +273,7 @@
 		p2.To.Type = obj.TYPE_BRANCH
 		p2.To.SetTarget(p)
 		// ISYNC
-		pisync := s.Prog(ppc64.AISYNC)
-		pisync.To.Type = obj.TYPE_NONE
+		s.Prog(ppc64.AISYNC)
 
 	case ssa.OpPPC64LoweredAtomicLoad8,
 		ssa.OpPPC64LoweredAtomicLoad32,
@@ -302,8 +297,7 @@
 		out := v.Reg0()
 		// SYNC when AuxInt == 1; otherwise, load-acquire
 		if v.AuxInt == 1 {
-			psync := s.Prog(ppc64.ASYNC)
-			psync.To.Type = obj.TYPE_NONE
+			s.Prog(ppc64.ASYNC)
 		}
 		// Load
 		p := s.Prog(ld)
@@ -322,7 +316,6 @@
 		p2.To.Type = obj.TYPE_BRANCH
 		// ISYNC
 		pisync := s.Prog(ppc64.AISYNC)
-		pisync.To.Type = obj.TYPE_NONE
 		p2.To.SetTarget(pisync)
 
 	case ssa.OpPPC64LoweredAtomicStore8,
@@ -345,8 +338,7 @@
 		if v.AuxInt == 0 {
 			syncOp = ppc64.ALWSYNC
 		}
-		psync := s.Prog(syncOp)
-		psync.To.Type = obj.TYPE_NONE
+		s.Prog(syncOp)
 		// Store
 		p := s.Prog(st)
 		p.To.Type = obj.TYPE_MEM
@@ -387,8 +379,7 @@
 		p.To.Reg = out
 		// LWSYNC - Assuming shared data not write-through-required nor
 		// caching-inhibited. See Appendix B.2.2.2 in the ISA 2.07b.
-		plwsync1 := s.Prog(ppc64.ALWSYNC)
-		plwsync1.To.Type = obj.TYPE_NONE
+		s.Prog(ppc64.ALWSYNC)
 		// LDAR or LWAR
 		p0 := s.Prog(ld)
 		p0.From.Type = obj.TYPE_MEM
@@ -430,7 +421,6 @@
 		// If the operation is a CAS-Release, then synchronization is not necessary.
 		if v.AuxInt != 0 {
 			plwsync2 := s.Prog(ppc64.ALWSYNC)
-			plwsync2.To.Type = obj.TYPE_NONE
 			p2.To.SetTarget(plwsync2)
 		} else {
 			// done (label)

Change information

Files:

• M src/cmd/compile/internal/ppc64/ssa.go

Change size: S

Delta: 1 file changed, 9 insertions(+), 19 deletions(-)

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Gerrit

Gerrit-MessageType: newchange

Gerrit-Project: go

Gerrit-Branch: master

Gerrit-Change-Id: I5f1070bc5740c477654de10393d9c498ce257728

Gerrit-Change-Number: 787760

Gerrit-PatchSet: 1

Gerrit-Owner: Jorropo <jorro...@gmail.com>

Gerrit-Reviewer: Jorropo <jorro...@gmail.com>