cmd/internal/obj/loong64: add {,X}VSHUF.{H/W/V} instructions support
Go asm syntax:
VSHUF{H/W/V} V1, V2, V3
XVSHUF{H/W/V} X1, X2, X3
Equivalent platform assembler syntax:
vshuf.{h/w/d} v3, v1, v2
xvshuf.{h/w/d} x3, x1, x2diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
index b440a64..f8105d6 100644
--- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s
+++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s
@@ -1023,6 +1023,14 @@
XVSHUF4IV $8, X1, X2 // 22209c77
XVSHUF4IV $15, X1, X2 // 223c9c77
+ // [X]VSHUF.{H/W/V} instructions
+ VSHUFH V1, V2, V3 // 43847a71
+ VSHUFW V1, V2, V3 // 43047b71
+ VSHUFV V1, V2, V3 // 43847b71
+ XVSHUFH X1, X2, X3 // 43847a75
+ XVSHUFW X1, X2, X3 // 43047b75
+ XVSHUFV X1, X2, X3 // 43847b75
+
// VPERMIW, XVPERMI{W,V,Q} instructions
VPERMIW $0x1B, V1, V2 // VPERMIW $27, V1, V2 // 226ce473
XVPERMIW $0x2B, X1, X2 // XVPERMIW $43, X1, X2 // 22ace477
diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go
index 48e60b6..d19809b 100644
--- a/src/cmd/internal/obj/loong64/a.out.go
+++ b/src/cmd/internal/obj/loong64/a.out.go
@@ -1115,6 +1115,13 @@
AXVSHUF4IW
AXVSHUF4IV
+ AVSHUFH
+ AVSHUFW
+ AVSHUFV
+ AXVSHUFH
+ AXVSHUFW
+ AXVSHUFV
+
AVPERMIW
AXVPERMIW
AXVPERMIV
diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go
index 9580674..5a32c2c 100644
--- a/src/cmd/internal/obj/loong64/anames.go
+++ b/src/cmd/internal/obj/loong64/anames.go
@@ -586,6 +586,12 @@
"XVSHUF4IH",
"XVSHUF4IW",
"XVSHUF4IV",
+ "VSHUFH",
+ "VSHUFW",
+ "VSHUFV",
+ "XVSHUFH",
+ "XVSHUFW",
+ "XVSHUFV",
"VPERMIW",
"XVPERMIW",
"XVPERMIV",
diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go
index 8bf8a1d..00f90c0 100644
--- a/src/cmd/internal/obj/loong64/asm.go
+++ b/src/cmd/internal/obj/loong64/asm.go
@@ -1698,6 +1698,9 @@
opset(AVMULD, r0)
opset(AVDIVF, r0)
opset(AVDIVD, r0)
+ opset(AVSHUFH, r0)
+ opset(AVSHUFW, r0)
+ opset(AVSHUFV, r0)
case AXVSEQB:
opset(AXVSEQH, r0)
@@ -1771,6 +1774,9 @@
opset(AXVMULD, r0)
opset(AXVDIVF, r0)
opset(AXVDIVD, r0)
+ opset(AXVSHUFH, r0)
+ opset(AXVSHUFW, r0)
+ opset(AXVSHUFV, r0)
case AVANDB:
opset(AVORB, r0)
@@ -3775,6 +3781,18 @@
return 0xea22 << 15 // xvbitrev.w
case AXVBITREVV:
return 0xea23 << 15 // xvbitrev.d
+ case AVSHUFH:
+ return 0x0E2F5 << 15 // vshuf.h
+ case AVSHUFW:
+ return 0x0E2F6 << 15 // vshuf.w
+ case AVSHUFV:
+ return 0x0E2F7 << 15 // vshuf.d
+ case AXVSHUFH:
+ return 0x0EAF5 << 15 // xvshuf.h
+ case AXVSHUFW:
+ return 0x0EAF6 << 15 // xvshuf.w
+ case AXVSHUFV:
+ return 0x0EAF7 << 15 // xvshuf.d
}
if a < 0 {
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vshuf.{h/w/d} v3, v1, v2The register order is wrong.
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The register order is wrong.
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2 is the latest approved patch-set.
The change was submitted with unreviewed changes in the following files:
```
The name of the file: src/cmd/internal/obj/loong64/anames.go
Insertions: 2, Deletions: 0.
@@ -586,9 +586,11 @@
"XVSHUF4IH",
"XVSHUF4IW",
"XVSHUF4IV",
+ "VSHUFB",
"VSHUFH",
"VSHUFW",
"VSHUFV",
+ "XVSHUFB",
"XVSHUFH",
"XVSHUFW",
"XVSHUFV",
```
```
The name of the file: src/cmd/internal/obj/loong64/a.out.go
Insertions: 2, Deletions: 0.
@@ -1115,9 +1115,11 @@
AXVSHUF4IW
AXVSHUF4IV
+ AVSHUFB
AVSHUFH
AVSHUFW
AVSHUFV
+ AXVSHUFB
AXVSHUFH
AXVSHUFW
AXVSHUFV
```
```
The name of the file: src/cmd/asm/internal/asm/testdata/loong64enc1.s
Insertions: 3, Deletions: 1.
@@ -1023,13 +1023,15 @@
XVSHUF4IV $8, X1, X2 // 22209c77
XVSHUF4IV $15, X1, X2 // 223c9c77
- // [X]VSHUF.{H/W/V} instructions
+ // [X]VSHUF.{B/H/W/V} instructions
VSHUFH V1, V2, V3 // 43847a71
VSHUFW V1, V2, V3 // 43047b71
VSHUFV V1, V2, V3 // 43847b71
XVSHUFH X1, X2, X3 // 43847a75
XVSHUFW X1, X2, X3 // 43047b75
XVSHUFV X1, X2, X3 // 43847b75
+ VSHUFB V1, V2, V3, V4 // 6488500d
+ XVSHUFB X1, X2, X3, X4 // 6488600d
// VPERMIW, XVPERMI{W,V,Q} instructions
VPERMIW $0x1B, V1, V2 // VPERMIW $27, V1, V2 // 226ce473
```
```
The name of the file: src/cmd/internal/obj/loong64/asm.go
Insertions: 8, Deletions: 0.
@@ -155,6 +155,8 @@
{AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
{AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
+ {AVSHUFB, C_VREG, C_VREG, C_VREG, C_VREG, C_NONE, 37, 4, 0, 0},
+ {AXVSHUFB, C_XREG, C_XREG, C_XREG, C_XREG, C_NONE, 37, 4, 0, 0},
{AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
{AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
@@ -1561,6 +1563,8 @@
AMOVWU,
AVMOVQ,
AXVMOVQ,
+ AVSHUFB,
+ AXVSHUFB,
ANEGW,
ANEGV,
AWORD,
@@ -3105,6 +3109,10 @@
return 0x8d << 20 // fnmsub.s
case AFNMSUBD:
return 0x8e << 20 // fnmsub.d
+ case AVSHUFB:
+ return 0x0D5 << 20 // vshuf.b
+ case AXVSHUFB:
+ return 0x0D6 << 20 // xvshuf.b
}
c.ctxt.Diag("bad rrrr opcode %v", a)
```
cmd/internal/obj/loong64: add {,X}VSHUF.{B/H/W/V} instructions support
Go asm syntax:
VSHUFB V1, V2, V3, V4
XVSHUFB X1, X2, X3, X4
VSHUF{H/W/V} V1, V2, V3
XVSHUF{H/W/V} X1, X2, X3
Equivalent platform assembler syntax:
vshuf.b v4, v3, v2, v1
xvshuf.b x4, x3, x2, x1
vshuf.{h/w/d} v3, v2, v1
xvshuf.{h/w/d} x3, x2, x1
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