[go] runtime, cmd/internal/obj/riscv: enable framepointer on riscv64
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Boyao Wang (Gerrit)
Mar 9, 2026, 8:21:12 AM (9 days ago) Mar 9
to goph...@pubsubhelper.golang.org, golang-co...@googlegroups.com
Boyao Wang has uploaded the change for review![]( "Open in Gerrit")
Commit message
runtime, cmd/internal/obj/riscv: enable framepointer on riscv64
This CL implements hardware frame pointer support for riscv64.
The stack layout is similar to arm64, but with the following specifics:
- The FP register points to SP+8.
- The return address (LR) is stored at SP.
- The caller's FP is stored at SP-8.
Change-Id: I3bc7af2abb024ea0b0e3432ed517641c6707f7a2
Change diff
diff --git a/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go b/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
index d81b533..0a40f80 100644
--- a/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
@@ -28,6 +28,7 @@
riscv64REG_SP = 2
riscv64REG_GP = 3
riscv64REG_TP = 4
+ riscv64REG_FP = 8
riscv64REG_TMP = 31
riscv64REG_ZERO = 0
)
@@ -79,7 +80,7 @@
// Add general purpose registers to gpMask.
switch r {
// ZERO, GP, TP and TMP are not in any gp mask.
- case riscv64REG_ZERO, riscv64REG_GP, riscv64REG_TP, riscv64REG_TMP:
+ case riscv64REG_ZERO, riscv64REG_GP, riscv64REG_TP, riscv64REG_TMP, riscv64REG_FP:
case riscv64REG_G:
gpgMask |= mask
gpspsbgMask |= mask
@@ -560,9 +561,9 @@
regnames: regNamesRISCV64,
gpregmask: gpMask,
fpregmask: fpMask,
- framepointerreg: -1, // not used
- // Integer parameters passed in register X10-X17, X8-X9, X18-X23
- ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X8 X9 X18 X19 X20 X21 X22 X23",
+ framepointerreg: 7, // Frame Pointer of RISCV is X8
+ // Integer parameters passed in register X10-X17, X9, X18-X23
+ ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X9 X18 X19 X20 X21 X22 X23",
// Float parameters passed in register F10-F17, F8-F9, F18-F23
ParamFloatRegNames: "F10 F11 F12 F13 F14 F15 F16 F17 F8 F9 F18 F19 F20 F21 F22 F23",
})
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 96bb288..4697af4 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -79178,11 +79178,11 @@
asm: riscv.AADD,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79193,10 +79193,10 @@
asm: riscv.AADDI,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79207,10 +79207,10 @@
asm: riscv.AADDIW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79220,10 +79220,10 @@
asm: riscv.ANEG,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79233,10 +79233,10 @@
asm: riscv.ANEGW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79246,11 +79246,11 @@
asm: riscv.ASUB,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79260,11 +79260,11 @@
asm: riscv.ASUBW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79275,11 +79275,11 @@
asm: riscv.AMUL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79290,11 +79290,11 @@
asm: riscv.AMULW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79305,11 +79305,11 @@
asm: riscv.AMULH,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79320,11 +79320,11 @@
asm: riscv.AMULHU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79334,12 +79334,12 @@
resultNotInArgs: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79349,12 +79349,12 @@
resultNotInArgs: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79364,11 +79364,11 @@
asm: riscv.ADIV,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79378,11 +79378,11 @@
asm: riscv.ADIVU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79392,11 +79392,11 @@
asm: riscv.ADIVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79406,11 +79406,11 @@
asm: riscv.ADIVUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79420,11 +79420,11 @@
asm: riscv.AREM,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79434,11 +79434,11 @@
asm: riscv.AREMU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79448,11 +79448,11 @@
asm: riscv.AREMW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79462,11 +79462,11 @@
asm: riscv.AREMUW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79479,10 +79479,10 @@
asm: riscv.AMOV,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79494,7 +79494,7 @@
asm: riscv.AMOV,
reg: regInfo{
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79531,10 +79531,10 @@
asm: riscv.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79547,10 +79547,10 @@
asm: riscv.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79563,10 +79563,10 @@
asm: riscv.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79579,10 +79579,10 @@
asm: riscv.AMOV,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79595,10 +79595,10 @@
asm: riscv.AMOVBU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79611,10 +79611,10 @@
asm: riscv.AMOVHU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79627,10 +79627,10 @@
asm: riscv.AMOVWU,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79643,8 +79643,8 @@
asm: riscv.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79657,8 +79657,8 @@
asm: riscv.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79671,8 +79671,8 @@
asm: riscv.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79685,8 +79685,8 @@
asm: riscv.AMOV,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79699,7 +79699,7 @@
asm: riscv.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79712,7 +79712,7 @@
asm: riscv.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79725,7 +79725,7 @@
asm: riscv.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79738,7 +79738,7 @@
asm: riscv.AMOV,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -79748,10 +79748,10 @@
asm: riscv.AMOVB,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79761,10 +79761,10 @@
asm: riscv.AMOVH,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79774,10 +79774,10 @@
asm: riscv.AMOVW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79787,10 +79787,10 @@
asm: riscv.AMOV,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79800,10 +79800,10 @@
asm: riscv.AMOVBU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79813,10 +79813,10 @@
asm: riscv.AMOVHU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79826,10 +79826,10 @@
asm: riscv.AMOVWU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79839,10 +79839,10 @@
resultInArg0: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79852,11 +79852,11 @@
asm: riscv.ASLL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79866,11 +79866,11 @@
asm: riscv.ASLLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79880,11 +79880,11 @@
asm: riscv.ASRA,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79894,11 +79894,11 @@
asm: riscv.ASRAW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79908,11 +79908,11 @@
asm: riscv.ASRL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79922,11 +79922,11 @@
asm: riscv.ASRLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79937,10 +79937,10 @@
asm: riscv.ASLLI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79951,10 +79951,10 @@
asm: riscv.ASLLIW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79965,10 +79965,10 @@
asm: riscv.ASRAI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79979,10 +79979,10 @@
asm: riscv.ASRAIW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -79993,10 +79993,10 @@
asm: riscv.ASRLI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80007,10 +80007,10 @@
asm: riscv.ASRLIW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80020,11 +80020,11 @@
asm: riscv.ASH1ADD,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80034,11 +80034,11 @@
asm: riscv.ASH2ADD,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80048,11 +80048,11 @@
asm: riscv.ASH3ADD,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80063,11 +80063,11 @@
asm: riscv.AAND,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80077,11 +80077,11 @@
asm: riscv.AANDN,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80092,10 +80092,10 @@
asm: riscv.AANDI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80105,10 +80105,10 @@
asm: riscv.ACLZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80118,10 +80118,10 @@
asm: riscv.ACLZW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80131,10 +80131,10 @@
asm: riscv.ACPOP,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80144,10 +80144,10 @@
asm: riscv.ACPOPW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80157,10 +80157,10 @@
asm: riscv.ACTZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80170,10 +80170,10 @@
asm: riscv.ACTZW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80183,10 +80183,10 @@
asm: riscv.ANOT,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80197,11 +80197,11 @@
asm: riscv.AOR,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80211,11 +80211,11 @@
asm: riscv.AORN,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80226,10 +80226,10 @@
asm: riscv.AORI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80239,10 +80239,10 @@
asm: riscv.AREV8,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80252,11 +80252,11 @@
asm: riscv.AROL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80266,11 +80266,11 @@
asm: riscv.AROLW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80280,11 +80280,11 @@
asm: riscv.AROR,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80295,10 +80295,10 @@
asm: riscv.ARORI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80309,10 +80309,10 @@
asm: riscv.ARORIW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80322,11 +80322,11 @@
asm: riscv.ARORW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80337,11 +80337,11 @@
asm: riscv.AXNOR,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80352,11 +80352,11 @@
asm: riscv.AXOR,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80367,10 +80367,10 @@
asm: riscv.AXORI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80381,11 +80381,11 @@
asm: riscv.AMIN,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80396,11 +80396,11 @@
asm: riscv.AMAX,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80411,11 +80411,11 @@
asm: riscv.AMINU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80426,11 +80426,11 @@
asm: riscv.AMAXU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80440,10 +80440,10 @@
asm: riscv.ASEQZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80453,10 +80453,10 @@
asm: riscv.ASNEZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80466,11 +80466,11 @@
asm: riscv.ASLT,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80481,10 +80481,10 @@
asm: riscv.ASLTI,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80494,11 +80494,11 @@
asm: riscv.ASLTU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80509,10 +80509,10 @@
asm: riscv.ASLTIU,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80548,7 +80548,7 @@
argLen: -1,
call: true,
reg: regInfo{
- clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+ clobbers: 9223372035781033840, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
@@ -80558,7 +80558,7 @@
call: true,
tailCall: true,
reg: regInfo{
- clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+ clobbers: 9223372035781033840, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
@@ -80582,9 +80582,9 @@
reg: regInfo{
inputs: []inputInfo{
{1, 33554432}, // X26
- {0, 1006632930}, // SP X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632802}, // SP X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
- clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+ clobbers: 9223372035781033840, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
@@ -80594,9 +80594,9 @@
call: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632800}, // X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
- clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
+ clobbers: 9223372035781033840, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
{
@@ -80607,7 +80607,7 @@
symEffect: SymWrite,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80620,7 +80620,7 @@
symEffect: SymWrite,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
clobbersArg0: true,
},
@@ -80634,8 +80634,8 @@
symEffect: SymWrite,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632800}, // X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632800}, // X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
clobbers: 16, // X5
},
@@ -80649,8 +80649,8 @@
symEffect: SymWrite,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632768}, // X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632768}, // X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
clobbers: 48, // X5 X6
clobbersArg0: true,
@@ -80663,10 +80663,10 @@
faultOnNilArg0: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80676,10 +80676,10 @@
faultOnNilArg0: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80689,10 +80689,10 @@
faultOnNilArg0: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80703,8 +80703,8 @@
hasSideEffects: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -80715,8 +80715,8 @@
hasSideEffects: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -80727,8 +80727,8 @@
hasSideEffects: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {1, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
},
},
@@ -80740,11 +80740,11 @@
hasSideEffects: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80756,11 +80756,11 @@
hasSideEffects: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80773,11 +80773,11 @@
unsafePoint: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80790,11 +80790,11 @@
unsafePoint: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80807,12 +80807,12 @@
unsafePoint: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {2, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80825,12 +80825,12 @@
unsafePoint: true,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {2, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80842,8 +80842,8 @@
asm: riscv.AAMOANDW,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
},
},
@@ -80855,8 +80855,8 @@
asm: riscv.AAMOORW,
reg: regInfo{
inputs: []inputInfo{
- {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
- {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
+ {1, 1073741680}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
+ {0, 9223372037928517490}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
},
},
},
@@ -80867,7 +80867,7 @@
faultOnNilArg0: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632818}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80886,7 +80886,7 @@
rematerializeable: true,
reg: regInfo{
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80896,7 +80896,7 @@
rematerializeable: true,
reg: regInfo{
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -80926,8 +80926,8 @@
call: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
- {1, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
+ {0, 1048432}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
+ {1, 1048432}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
},
},
},
@@ -80938,7 +80938,7 @@
call: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
+ {0, 1048432}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
},
},
},
@@ -80949,7 +80949,7 @@
call: true,
reg: regInfo{
inputs: []inputInfo{
- {0, 1048560}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
+ {0, 1048432}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
},
},
},
@@ -81114,7 +81114,7 @@
asm: riscv.AFMVSX,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81130,7 +81130,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81140,7 +81140,7 @@
asm: riscv.AFCVTSW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81153,7 +81153,7 @@
asm: riscv.AFCVTSL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81169,7 +81169,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81182,7 +81182,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81195,7 +81195,7 @@
asm: riscv.AMOVF,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81211,7 +81211,7 @@
asm: riscv.AMOVF,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
@@ -81227,7 +81227,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81242,7 +81242,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81256,7 +81256,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81270,7 +81270,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81487,7 +81487,7 @@
asm: riscv.AFMVDX,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81503,7 +81503,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81513,7 +81513,7 @@
asm: riscv.AFCVTDW,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81526,7 +81526,7 @@
asm: riscv.AFCVTDL,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81542,7 +81542,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81555,7 +81555,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81594,7 +81594,7 @@
asm: riscv.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
},
outputs: []outputInfo{
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@@ -81610,7 +81610,7 @@
asm: riscv.AMOVD,
reg: regInfo{
inputs: []inputInfo{
- {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
+ {0, 9223372037861408626}, // SP X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
},
@@ -81626,7 +81626,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81641,7 +81641,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81655,7 +81655,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81669,7 +81669,7 @@
{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81714,7 +81714,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81727,7 +81727,7 @@
{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81737,11 +81737,11 @@
asm: riscv.ACZEROEQZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -81751,11 +81751,11 @@
asm: riscv.ACZERONEZ,
reg: regInfo{
inputs: []inputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
- {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {1, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
outputs: []outputInfo{
- {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
+ {0, 1006632816}, // X5 X6 X7 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
},
},
@@ -96934,12 +96934,12 @@
{62, riscv.REG_F31, "F31"},
{63, 0, "SB"},
}
-var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22}
+var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 8, 17, 18, 19, 20, 21, 22}
var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54}
-var gpRegMaskRISCV64 = regMask(1006632944)
+var gpRegMaskRISCV64 = regMask(1006632816)
var fpRegMaskRISCV64 = regMask(9223372034707292160)
var specialRegMaskRISCV64 = regMask(0)
-var framepointerRegRISCV64 = int8(-1)
+var framepointerRegRISCV64 = int8(7)
var linkRegRISCV64 = int8(0)
var registersS390X = [...]Register{
{0, s390x.REG_R0, "R0"},
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index e9005fe..96c4023 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -454,14 +454,14 @@
//
// A nicer version of this diagram can be found on slide 21 of the presentation
// attached to https://golang.org/issue/16922#issuecomment-243748180.
-func stackOffset(a *obj.Addr, stacksize int64) {
+func stackOffset(a *obj.Addr, stacksize int64, framesize int64) {
switch a.Name {
case obj.NAME_AUTO:
// Adjust to the top of AUTOs.
a.Offset += stacksize
case obj.NAME_PARAM:
// Adjust to the bottom of PARAMs.
- a.Offset += stacksize + 8
+ a.Offset += framesize + 8
}
}
@@ -513,18 +513,30 @@
stacksize += ctxt.Arch.FixedFrameSize
}
+ // If the function has a frame, build an frame record.
+ //
+ // After the frame is created, FP points to 8(SP), SP points to the saved
+ // return address (RA/LR) at 0(SP), and the saved frame pointer (caller S0)
+ // is placed just below it at -PtrSize(SP).
+ useFP := buildcfg.FramePointerEnabled && stacksize != 0
+ framesize := stacksize
+ if useFP {
+ framesize += int64(ctxt.Arch.PtrSize)
+ }
cursym.Func().Args = text.To.Val.(int32)
cursym.Func().Locals = int32(stacksize)
prologue := text
if !cursym.Func().Text.From.Sym.NoSplit() {
- prologue = stacksplit(ctxt, prologue, cursym, newprog, stacksize) // emit split check
+ prologue = stacksplit(ctxt, prologue, cursym, newprog, framesize) // emit split check
}
q := prologue
if stacksize != 0 {
+ var prologueEnd *obj.Prog
+
prologue = ctxt.StartUnsafePoint(prologue, newprog)
// Actually save LR.
@@ -532,35 +544,62 @@
prologue.As = AMOV
prologue.Pos = q.Pos
prologue.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR}
- prologue.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -stacksize}
+ prologue.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -framesize}
+
+ if useFP {
+ // Save caller's frame pointer (S0) in the caller frame slot,
+ // one word below the stack pointer.
+ prologue = obj.Appendp(prologue, newprog)
+ prologue.As = AMOV
+ prologue.Pos = q.Pos
+ prologue.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
+ prologue.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -framesize - int64(ctxt.Arch.PtrSize)}
+ }
// Insert stack adjustment.
prologue = obj.Appendp(prologue, newprog)
prologue.As = AADDI
prologue.Pos = q.Pos
- prologue.Pos = prologue.Pos.WithXlogue(src.PosPrologueEnd)
- prologue.From = obj.Addr{Type: obj.TYPE_CONST, Offset: -stacksize}
+ prologue.From = obj.Addr{Type: obj.TYPE_CONST, Offset: -framesize}
prologue.Reg = REG_SP
prologue.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_SP}
- prologue.Spadj = int32(stacksize)
-
- prologue = ctxt.EndUnsafePoint(prologue, newprog, -1)
+ prologue.Spadj = int32(framesize)
// On Linux, in a cgo binary we may get a SIGSETXID signal early on
// before the signal stack is set, as glibc doesn't allow us to block
// SIGSETXID. So a signal may land on the current stack and clobber
- // the content below the SP. We store the LR again after the SP is
- // decremented.
+ // the content below the SP. Store the LR and FP again after the SP
+ // is decremented.
prologue = obj.Appendp(prologue, newprog)
prologue.As = AMOV
prologue.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR}
prologue.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: 0}
+ prologueEnd = prologue
+
+ if useFP {
+ prologue = obj.Appendp(prologue, newprog)
+ prologue.As = AMOV
+ prologue.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
+ prologue.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -int64(ctxt.Arch.PtrSize)}
+
+ prologue = obj.Appendp(prologue, newprog)
+ prologue.As = AADDI
+ prologue.Pos = q.Pos
+ prologue.From = obj.Addr{Type: obj.TYPE_CONST, Offset: int64(ctxt.Arch.PtrSize)}
+ prologue.Reg = REG_SP
+ prologue.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
+ prologueEnd = prologue
+ }
+
+ // End the async-unsafe region only once the frame record is complete.
+ ctxt.EndUnsafePoint(prologueEnd, newprog, -1)
+ prologueEnd.Pos = prologueEnd.Pos.WithXlogue(src.PosPrologueEnd)
}
// Update stack-based offsets.
for p := cursym.Func().Text; p != nil; p = p.Link {
- stackOffset(&p.From, stacksize)
- stackOffset(&p.To, stacksize)
+ stackOffset(&p.From, stacksize, framesize)
+ stackOffset(&p.To, stacksize, framesize)
}
// Additional instruction rewriting.
@@ -602,6 +641,14 @@
}
if stacksize != 0 {
+ if useFP {
+ // Restore S0.
+ p.As = AMOV
+ p.From = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -int64(ctxt.Arch.PtrSize)}
+ p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
+ p = obj.Appendp(p, newprog)
+ }
+
// Restore LR.
p.As = AMOV
p.From = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: 0}
@@ -609,10 +656,10 @@
p = obj.Appendp(p, newprog)
p.As = AADDI
- p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: stacksize}
+ p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: framesize}
p.Reg = REG_SP
p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_SP}
- p.Spadj = int32(-stacksize)
+ p.Spadj = int32(-framesize)
p = obj.Appendp(p, newprog)
}
@@ -633,7 +680,7 @@
// Spadj from function entry to each PC, and shouldn't
// count adjustments from earlier epilogues, since they
// won't affect later PCs.
- p.Spadj = int32(stacksize)
+ p.Spadj = int32(framesize)
case AADDI:
// Refine Spadjs account for adjustment via ADDI instruction.
@@ -821,26 +868,37 @@
}
if ctxt.Flag_maymorestack != "" {
- // Save LR and REGCTXT
- const frameSize = 16
+ // Save LR FP and REGCTXT
+ const frameSize = 32
p = ctxt.StartUnsafePoint(p, newprog)
// Spill Arguments. This has to happen before we open
// any more frame space.
p = cursym.Func().SpillRegisterArgs(p, newprog)
- // MOV LR, -16(SP)
+ // MOV LR, -32(SP)
p = obj.Appendp(p, newprog)
p.As = AMOV
p.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR}
p.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -frameSize}
- // ADDI $-16, SP
+ // ADDI $-32, SP
p = obj.Appendp(p, newprog)
p.As = AADDI
p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: -frameSize}
p.Reg = REG_SP
p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_SP}
p.Spadj = frameSize
+ // MOV S0, -8(SP)
+ p = obj.Appendp(p, newprog)
+ p.As = AMOV
+ p.From = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
+ p.To = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -int64(ctxt.Arch.PtrSize)}
+ // ADDI $8, SP, S0
+ p = obj.Appendp(p, newprog)
+ p.As = AADDI
+ p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: int64(ctxt.Arch.PtrSize)}
+ p.Reg = REG_SP
+ p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
// MOV REGCTXT, 8(SP)
p = obj.Appendp(p, newprog)
p.As = AMOV
@@ -855,19 +913,24 @@
p.To.Sym = ctxt.LookupABI(ctxt.Flag_maymorestack, cursym.ABI())
jalToSym(ctxt, p, REG_X5)
- // Restore LR and REGCTXT
+ // Restore LR FP and REGCTXT
// MOV 8(SP), REGCTXT
p = obj.Appendp(p, newprog)
p.As = AMOV
p.From = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: 8}
p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_CTXT}
+ // MOV -8(SP), S0
+ p = obj.Appendp(p, newprog)
+ p.As = AMOV
+ p.From = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: -int64(ctxt.Arch.PtrSize)}
+ p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_S0}
// MOV (SP), LR
p = obj.Appendp(p, newprog)
p.As = AMOV
p.From = obj.Addr{Type: obj.TYPE_MEM, Reg: REG_SP, Offset: 0}
p.To = obj.Addr{Type: obj.TYPE_REG, Reg: REG_LR}
- // ADDI $16, SP
+ // ADDI $32, SP
p = obj.Appendp(p, newprog)
p.As = AADDI
p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: frameSize}
diff --git a/src/crypto/internal/fips140/bigmod/nat_riscv64.s b/src/crypto/internal/fips140/bigmod/nat_riscv64.s
index c1d9cc0..66780d4 100644
--- a/src/crypto/internal/fips140/bigmod/nat_riscv64.s
+++ b/src/crypto/internal/fips140/bigmod/nat_riscv64.s
@@ -34,15 +34,15 @@
MOV 2*8(X5), X16 // z[2]
MOV 3*8(X5), X19 // z[3]
- MOV 0*8(X7), X8 // x[0]
+ MOV 0*8(X7), X20 // x[0]
MOV 1*8(X7), X11 // x[1]
MOV 2*8(X7), X14 // x[2]
MOV 3*8(X7), X17 // x[3]
- MULHU X8, X6, X9 // z_hi[0] = x[0] * y
- MUL X8, X6, X8 // z_lo[0] = x[0] * y
- ADD X8, X10, X21 // z_lo[0] = x[0] * y + z[0]
- SLTU X8, X21, X22
+ MULHU X20, X6, X9 // z_hi[0] = x[0] * y
+ MUL X20, X6, X20 // z_lo[0] = x[0] * y
+ ADD X20, X10, X21 // z_lo[0] = x[0] * y + z[0]
+ SLTU X20, X21, X22
ADD X9, X22, X9 // z_hi[0] = x[0] * y + z[0]
ADD X21, X29, X10 // z_lo[0] = x[0] * y + z[0] + c
SLTU X21, X10, X22
diff --git a/src/crypto/internal/fips140/sha256/sha256block_riscv64.s b/src/crypto/internal/fips140/sha256/sha256block_riscv64.s
index 567d447..7bd54d6 100644
--- a/src/crypto/internal/fips140/sha256/sha256block_riscv64.s
+++ b/src/crypto/internal/fips140/sha256/sha256block_riscv64.s
@@ -51,13 +51,13 @@
MOVBU ((index*4)+0)(X29), X5; \
MOVBU ((index*4)+1)(X29), X6; \
MOVBU ((index*4)+2)(X29), X7; \
- MOVBU ((index*4)+3)(X29), X8; \
+ MOVBU ((index*4)+3)(X29), X22; \
SLL $24, X5; \
SLL $16, X6; \
OR X5, X6, X5; \
SLL $8, X7; \
OR X5, X7, X5; \
- OR X5, X8, X5; \
+ OR X5, X22, X5; \
MOVW X5, (index*4)(X19)
// Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63
@@ -69,16 +69,16 @@
MOVWU (((index-7)&0xf)*4)(X19), X9; \
MOVWU (((index-16)&0xf)*4)(X19), X21; \
RORW $17, X5, X7; \
- RORW $19, X5, X8; \
+ RORW $19, X5, X22; \
SRL $10, X5; \
XOR X7, X5; \
- XOR X8, X5; \
+ XOR X22, X5; \
ADD X9, X5; \
RORW $7, X6, X7; \
- RORW $18, X6, X8; \
+ RORW $18, X6, X22; \
SRL $3, X6; \
XOR X7, X6; \
- XOR X8, X6; \
+ XOR X22, X6; \
ADD X6, X5; \
ADD X21, X5; \
MOVW X5, ((index&0xf)*4)(X19)
@@ -90,15 +90,15 @@
// Ch(x, y, z) = (x AND y) XOR (NOT x AND z)
// = ((y XOR z) AND x) XOR z
#define SHA256T1(index, e, f, g, h) \
- MOVWU (index*4)(X18), X8; \
+ MOVWU (index*4)(X18), X22; \
ADD X5, h; \
RORW $6, e, X6; \
- ADD X8, h; \
+ ADD X22, h; \
RORW $11, e, X7; \
- RORW $25, e, X8; \
+ RORW $25, e, X22; \
XOR X7, X6; \
XOR f, g, X5; \
- XOR X8, X6; \
+ XOR X22, X6; \
AND e, X5; \
ADD X6, h; \
XOR g, X5; \
@@ -112,12 +112,12 @@
#define SHA256T2(a, b, c) \
RORW $2, a, X6; \
RORW $13, a, X7; \
- RORW $22, a, X8; \
+ RORW $22, a, X22; \
XOR X7, X6; \
XOR b, c, X9; \
AND b, c, X7; \
AND a, X9; \
- XOR X8, X6; \
+ XOR X22, X6; \
XOR X7, X9; \
ADD X9, X6
@@ -233,11 +233,11 @@
MOVWU (0*4)(X20), X5
MOVWU (1*4)(X20), X6
MOVWU (2*4)(X20), X7
- MOVWU (3*4)(X20), X8
+ MOVWU (3*4)(X20), X22
ADD X5, X10 // H0 = a + H0
ADD X6, X11 // H1 = b + H1
ADD X7, X12 // H2 = c + H2
- ADD X8, X13 // H3 = d + H3
+ ADD X22, X13 // H3 = d + H3
MOVW X10, (0*4)(X20)
MOVW X11, (1*4)(X20)
MOVW X12, (2*4)(X20)
@@ -245,11 +245,11 @@
MOVWU (4*4)(X20), X5
MOVWU (5*4)(X20), X6
MOVWU (6*4)(X20), X7
- MOVWU (7*4)(X20), X8
+ MOVWU (7*4)(X20), X22
ADD X5, X14 // H4 = e + H4
ADD X6, X15 // H5 = f + H5
ADD X7, X16 // H6 = g + H6
- ADD X8, X17 // H7 = h + H7
+ ADD X22, X17 // H7 = h + H7
MOVW X14, (4*4)(X20)
MOVW X15, (5*4)(X20)
MOVW X16, (6*4)(X20)
diff --git a/src/crypto/internal/fips140/sha512/sha512block_riscv64.s b/src/crypto/internal/fips140/sha512/sha512block_riscv64.s
index f25ed62..9d665cc 100644
--- a/src/crypto/internal/fips140/sha512/sha512block_riscv64.s
+++ b/src/crypto/internal/fips140/sha512/sha512block_riscv64.s
@@ -51,25 +51,25 @@
MOVBU ((index*8)+0)(X29), X5; \
MOVBU ((index*8)+1)(X29), X6; \
MOVBU ((index*8)+2)(X29), X7; \
- MOVBU ((index*8)+3)(X29), X8; \
+ MOVBU ((index*8)+3)(X29), X22; \
SLL $56, X5; \
SLL $48, X6; \
OR X5, X6, X5; \
SLL $40, X7; \
OR X5, X7, X5; \
- SLL $32, X8; \
- OR X5, X8, X5; \
+ SLL $32, X22; \
+ OR X5, X22, X5; \
MOVBU ((index*8)+4)(X29), X9; \
MOVBU ((index*8)+5)(X29), X6; \
MOVBU ((index*8)+6)(X29), X7; \
- MOVBU ((index*8)+7)(X29), X8; \
+ MOVBU ((index*8)+7)(X29), X22; \
SLL $24, X9; \
OR X5, X9, X5; \
SLL $16, X6; \
OR X5, X6, X5; \
SLL $8, X7; \
OR X5, X7, X5; \
- OR X5, X8, X5; \
+ OR X5, X22, X5; \
MOV X5, (index*8)(X19)
// Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 79
@@ -81,16 +81,16 @@
MOV (((index-7)&0xf)*8)(X19), X9; \
MOV (((index-16)&0xf)*8)(X19), X21; \
ROR $19, X5, X7; \
- ROR $61, X5, X8; \
+ ROR $61, X5, X22; \
SRL $6, X5; \
XOR X7, X5; \
- XOR X8, X5; \
+ XOR X22, X5; \
ADD X9, X5; \
ROR $1, X6, X7; \
- ROR $8, X6, X8; \
+ ROR $8, X6, X22; \
SRL $7, X6; \
XOR X7, X6; \
- XOR X8, X6; \
+ XOR X22, X6; \
ADD X6, X5; \
ADD X21, X5; \
MOV X5, ((index&0xf)*8)(X19)
@@ -102,15 +102,15 @@
// Ch(x, y, z) = (x AND y) XOR (NOT x AND z)
// = ((y XOR z) AND x) XOR z
#define SHA512T1(index, e, f, g, h) \
- MOV (index*8)(X18), X8; \
+ MOV (index*8)(X18), X22; \
ADD X5, h; \
ROR $14, e, X6; \
- ADD X8, h; \
+ ADD X22, h; \
ROR $18, e, X7; \
- ROR $41, e, X8; \
+ ROR $41, e, X22; \
XOR X7, X6; \
XOR f, g, X5; \
- XOR X8, X6; \
+ XOR X22, X6; \
AND e, X5; \
ADD X6, h; \
XOR g, X5; \
@@ -124,12 +124,12 @@
#define SHA512T2(a, b, c) \
ROR $28, a, X6; \
ROR $34, a, X7; \
- ROR $39, a, X8; \
+ ROR $39, a, X22; \
XOR X7, X6; \
XOR b, c, X9; \
AND b, c, X7; \
AND a, X9; \
- XOR X8, X6; \
+ XOR X22, X6; \
XOR X7, X9; \
ADD X9, X6
@@ -258,11 +258,11 @@
MOV (0*8)(X20), X5
MOV (1*8)(X20), X6
MOV (2*8)(X20), X7
- MOV (3*8)(X20), X8
+ MOV (3*8)(X20), X22
ADD X5, X10 // H0 = a + H0
ADD X6, X11 // H1 = b + H1
ADD X7, X12 // H2 = c + H2
- ADD X8, X13 // H3 = d + H3
+ ADD X22, X13 // H3 = d + H3
MOV X10, (0*8)(X20)
MOV X11, (1*8)(X20)
MOV X12, (2*8)(X20)
@@ -270,11 +270,11 @@
MOV (4*8)(X20), X5
MOV (5*8)(X20), X6
MOV (6*8)(X20), X7
- MOV (7*8)(X20), X8
+ MOV (7*8)(X20), X22
ADD X5, X14 // H4 = e + H4
ADD X6, X15 // H5 = f + H5
ADD X7, X16 // H6 = g + H6
- ADD X8, X17 // H7 = h + H7
+ ADD X22, X17 // H7 = h + H7
MOV X14, (4*8)(X20)
MOV X15, (5*8)(X20)
MOV X16, (6*8)(X20)
diff --git a/src/crypto/internal/fips140/subtle/xor_riscv64.s b/src/crypto/internal/fips140/subtle/xor_riscv64.s
index 34331f9..7994a86 100644
--- a/src/crypto/internal/fips140/subtle/xor_riscv64.s
+++ b/src/crypto/internal/fips140/subtle/xor_riscv64.s
@@ -56,9 +56,9 @@
BEQZ X5, loop64_check
// Check one byte at a time until we reach 8 byte alignment.
- MOV $8, X8
- SUB X5, X8
- SUB X8, X13
+ MOV $8, X9
+ SUB X5, X9
+ SUB X9, X13
align:
MOVBU 0(X11), X16
MOVBU 0(X12), X17
@@ -67,8 +67,8 @@
ADD $1, X10
ADD $1, X11
ADD $1, X12
- SUB $1, X8
- BNEZ X8, align
+ SUB $1, X9
+ BNEZ X9, align
loop64_check:
MOV $64, X15
diff --git a/src/crypto/md5/md5block_riscv64.s b/src/crypto/md5/md5block_riscv64.s
index 017c70b..efd0730 100644
--- a/src/crypto/md5/md5block_riscv64.s
+++ b/src/crypto/md5/md5block_riscv64.s
@@ -162,7 +162,7 @@
LOAD64U(X29,0, X17, X18, X5)
LOAD64U(X29,8, X17, X18, X6)
LOAD64U(X29,16, X17, X18, X7)
- LOAD64U(X29,24, X17, X18, X8)
+ LOAD64U(X29,24, X17, X18, X21)
LOAD64U(X29,32, X17, X18, X9)
LOAD64U(X29,40, X17, X18, X10)
LOAD64U(X29,48, X17, X18, X11)
@@ -173,7 +173,7 @@
MOV (0*8)(X29), X5
MOV (1*8)(X29), X6
MOV (2*8)(X29), X7
- MOV (3*8)(X29), X8
+ MOV (3*8)(X29), X21
MOV (4*8)(X29), X9
MOV (5*8)(X29), X10
MOV (6*8)(X29), X11
@@ -200,8 +200,8 @@
ROUND1ODD(X14,X15,X16,X13,X6, -1044525330,22); // 0xc1bdceee
ROUND1EVN(X13,X14,X15,X16,X7, -176418897, 7); // 0xf57c0faf
ROUND1ODD(X16,X13,X14,X15,X7, 0x4787c62a,12); // 0x4787c62a
- ROUND1EVN(X15,X16,X13,X14,X8, -1473231341,17); // 0xa8304613
- ROUND1ODD(X14,X15,X16,X13,X8, -45705983,22); // 0xfd469501
+ ROUND1EVN(X15,X16,X13,X14,X21, -1473231341,17); // 0xa8304613
+ ROUND1ODD(X14,X15,X16,X13,X21, -45705983,22); // 0xfd469501
ROUND1EVN(X13,X14,X15,X16,X9, 0x698098d8, 7); // 0x698098d8
ROUND1ODD(X16,X13,X14,X15,X9, -1958414417,12); // 0x8b44f7af
ROUND1EVN(X15,X16,X13,X14,X10, -42063,17); // 0xffff5bb1
@@ -212,7 +212,7 @@
ROUND1ODD(X14,X15,X16,X13,X12, 0x49b40821,22); // 0x49b40821
ROUND2ODD(X13,X14,X15,X16,X5, -165796510, 5); // f61e2562
- ROUND2EVN(X16,X13,X14,X15,X8, -1069501632, 9); // c040b340
+ ROUND2EVN(X16,X13,X14,X15,X21, -1069501632, 9); // c040b340
ROUND2ODD(X15,X16,X13,X14,X10, 0x265e5a51,14); // 265e5a51
ROUND2EVN(X14,X15,X16,X13,X5, -373897302,20); // e9b6c7aa
ROUND2ODD(X13,X14,X15,X16,X7, -701558691, 5); // d62f105d
@@ -225,7 +225,7 @@
ROUND2EVN(X14,X15,X16,X13,X9, 0x455a14ed,20); // 455a14ed
ROUND2ODD(X13,X14,X15,X16,X11,-1444681467, 5); // a9e3e905
ROUND2EVN(X16,X13,X14,X15,X6, -51403784, 9); // fcefa3f8
- ROUND2ODD(X15,X16,X13,X14,X8, 0x676f02d9,14); // 676f02d9
+ ROUND2ODD(X15,X16,X13,X14,X21, 0x676f02d9,14); // 676f02d9
ROUND2EVN(X14,X15,X16,X13,X11,-1926607734,20); // 8d2a4c8a
ROUND3ODD(X13,X14,X15,X16,X7, -378558, 4); // fffa3942
@@ -234,19 +234,19 @@
ROUND3EVN(X14,X15,X16,X13,X12, -35309556,23); // fde5380c
ROUND3ODD(X13,X14,X15,X16,X5, -1530992060, 4); // a4beea44
ROUND3EVN(X16,X13,X14,X15,X7, 0x4bdecfa9,11); // 4bdecfa9
- ROUND3ODD(X15,X16,X13,X14,X8, -155497632,16); // f6bb4b60
+ ROUND3ODD(X15,X16,X13,X14,X21, -155497632,16); // f6bb4b60
ROUND3EVN(X14,X15,X16,X13,X10,-1094730640,23); // bebfbc70
ROUND3ODD(X13,X14,X15,X16,X11, 0x289b7ec6, 4); // 289b7ec6
ROUND3EVN(X16,X13,X14,X15,X5, -358537222,11); // eaa127fa
ROUND3ODD(X15,X16,X13,X14,X6, -722521979,16); // d4ef3085
- ROUND3EVN(X14,X15,X16,X13,X8, 0x4881d05,23); // 4881d05
+ ROUND3EVN(X14,X15,X16,X13,X21, 0x4881d05,23); // 4881d05
ROUND3ODD(X13,X14,X15,X16,X9, -640364487, 4); // d9d4d039
ROUND3EVN(X16,X13,X14,X15,X11, -421815835,11); // e6db99e5
ROUND3ODD(X15,X16,X13,X14,X12, 0x1fa27cf8,16); // 1fa27cf8
ROUND3EVN(X14,X15,X16,X13,X6, -995338651,23); // c4ac5665
ROUND4EVN(X13,X14,X15,X16,X5, -198630844, 6); // f4292244
- ROUND4ODD(X16,X13,X14,X15,X8, 0x432aff97,10); // 432aff97
+ ROUND4ODD(X16,X13,X14,X15,X21, 0x432aff97,10); // 432aff97
ROUND4EVN(X15,X16,X13,X14,X12,-1416354905,15); // ab9423a7
ROUND4ODD(X14,X15,X16,X13,X7, -57434055,21); // fc93a039
ROUND4EVN(X13,X14,X15,X16,X11, 0x655b59c3, 6); // 655b59c3
@@ -255,7 +255,7 @@
ROUND4ODD(X14,X15,X16,X13,X5, -2054922799,21); // 85845dd1
ROUND4EVN(X13,X14,X15,X16,X9, 0x6fa87e4f, 6); // 6fa87e4f
ROUND4ODD(X16,X13,X14,X15,X12, -30611744,10); // fe2ce6e0
- ROUND4EVN(X15,X16,X13,X14,X8, -1560198380,15); // a3014314
+ ROUND4EVN(X15,X16,X13,X14,X21, -1560198380,15); // a3014314
ROUND4ODD(X14,X15,X16,X13,X11, 0x4e0811a1,21); // 4e0811a1
ROUND4EVN(X13,X14,X15,X16,X7, -145523070, 6); // f7537e82
ROUND4ODD(X16,X13,X14,X15,X10,-1120210379,10); // bd3af235
diff --git a/src/crypto/sha1/sha1block_riscv64.s b/src/crypto/sha1/sha1block_riscv64.s
index 0849694..d41b452 100644
--- a/src/crypto/sha1/sha1block_riscv64.s
+++ b/src/crypto/sha1/sha1block_riscv64.s
@@ -10,23 +10,23 @@
MOVBU ((index*4)+0)(X29), X5; \
MOVBU ((index*4)+1)(X29), X6; \
MOVBU ((index*4)+2)(X29), X7; \
- MOVBU ((index*4)+3)(X29), X8; \
+ MOVBU ((index*4)+3)(X29), X9; \
SLL $24, X5; \
SLL $16, X6; \
OR X5, X6, X5; \
SLL $8, X7; \
OR X5, X7, X5; \
- OR X5, X8, X5; \
+ OR X5, X9, X5; \
MOVW X5, (index*4)(X19)
#define SHUFFLE(index) \
MOVWU (((index)&0xf)*4)(X19), X5; \
MOVWU (((index-3)&0xf)*4)(X19), X6; \
MOVWU (((index-8)&0xf)*4)(X19), X7; \
- MOVWU (((index-14)&0xf)*4)(X19), X8; \
+ MOVWU (((index-14)&0xf)*4)(X19), X9; \
XOR X6, X5; \
XOR X7, X5; \
- XOR X8, X5; \
+ XOR X9, X5; \
RORW $31, X5; \
MOVW X5, (((index)&0xf)*4)(X19)
@@ -43,20 +43,20 @@
// f = (b & c) | ((b | c) & d)
#define FUNC3(a, b, c, d, e) \
- OR b, c, X8; \
+ OR b, c, X9; \
AND b, c, X6; \
- AND d, X8; \
- OR X6, X8, X7
+ AND d, X9; \
+ OR X6, X9, X7
#define FUNC4 FUNC2
#define MIX(a, b, c, d, e, key) \
RORW $2, b; \
ADD X7, e; \
- RORW $27, a, X8; \
+ RORW $27, a, X9; \
ADD X5, e; \
ADD key, e; \
- ADD X8, e
+ ADD X9, e
#define ROUND1(a, b, c, d, e, index) \
LOAD(index); \
diff --git a/src/internal/abi/abi_riscv64.go b/src/internal/abi/abi_riscv64.go
index 2bcd9d6..b0b02d7 100644
--- a/src/internal/abi/abi_riscv64.go
+++ b/src/internal/abi/abi_riscv64.go
@@ -7,8 +7,8 @@
const (
// See abi_generic.go.
- // X8 - X23
- IntArgRegs = 16
+ // X10 - X17, X9, X18 - X23.
+ IntArgRegs = 15
// F8 - F23.
FloatArgRegs = 16
diff --git a/src/internal/buildcfg/exp.go b/src/internal/buildcfg/exp.go
index aa41986..b37f5092 100644
--- a/src/internal/buildcfg/exp.go
+++ b/src/internal/buildcfg/exp.go
@@ -48,7 +48,7 @@
// platforms that support it.
//
// Note: must agree with runtime.framepointer_enabled.
-var FramePointerEnabled = GOARCH == "amd64" || GOARCH == "arm64"
+var FramePointerEnabled = GOARCH == "amd64" || GOARCH == "arm64" || GOARCH == "riscv64"
// ParseGOEXPERIMENT parses a (GOOS, GOARCH, GOEXPERIMENT)
// configuration tuple and returns the enabled and baseline experiment
diff --git a/src/internal/bytealg/compare_riscv64.s b/src/internal/bytealg/compare_riscv64.s
index 3b1523d..2a02ca2 100644
--- a/src/internal/bytealg/compare_riscv64.s
+++ b/src/internal/bytealg/compare_riscv64.s
@@ -68,10 +68,10 @@
JMP cmp_len
vector_not_eq:
- // Load first differing bytes in X8/X9.
+ // Load first differing bytes in X14/X9.
ADD X7, X10
ADD X7, X12
- MOVBU (X10), X8
+ MOVBU (X10), X14
MOVBU (X12), X9
JMP cmp
@@ -81,8 +81,8 @@
// Check alignment - if alignment differs we have to do one byte at a time.
AND $7, X10, X7
- AND $7, X12, X8
- BNE X7, X8, check8_unaligned
+ AND $7, X12, X14
+ BNE X7, X14, check8_unaligned
BEQZ X7, compare32
// Check one byte at a time until we reach 8 byte alignment.
@@ -91,9 +91,9 @@
SUB X7, X5, X5
align:
SUB $1, X7
- MOVBU 0(X10), X8
+ MOVBU 0(X10), X14
MOVBU 0(X12), X9
- BNE X8, X9, cmp
+ BNE X14, X9, cmp
ADD $1, X10
ADD $1, X12
BNEZ X7, align
@@ -139,7 +139,7 @@
MOV $8, X6
BLT X5, X6, check4_unaligned
compare8_unaligned:
- MOVBU 0(X10), X8
+ MOVBU 0(X10), X14
MOVBU 1(X10), X15
MOVBU 2(X10), X17
MOVBU 3(X10), X19
@@ -155,7 +155,7 @@
MOVBU 5(X12), X24
MOVBU 6(X12), X28
MOVBU 7(X12), X30
- BNE X8, X9, cmp1a
+ BNE X14, X9, cmp1a
BNE X15, X16, cmp1b
BNE X17, X18, cmp1c
BNE X19, X20, cmp1d
@@ -173,7 +173,7 @@
MOV $4, X6
BLT X5, X6, compare1
compare4_unaligned:
- MOVBU 0(X10), X8
+ MOVBU 0(X10), X14
MOVBU 1(X10), X15
MOVBU 2(X10), X17
MOVBU 3(X10), X19
@@ -181,7 +181,7 @@
MOVBU 1(X12), X16
MOVBU 2(X12), X18
MOVBU 3(X12), X20
- BNE X8, X9, cmp1a
+ BNE X14, X9, cmp1a
BNE X15, X16, cmp1b
BNE X17, X18, cmp1c
BNE X19, X20, cmp1d
@@ -192,9 +192,9 @@
compare1:
BEQZ X5, cmp_len
- MOVBU 0(X10), X8
+ MOVBU 0(X10), X14
MOVBU 0(X12), X9
- BNE X8, X9, cmp
+ BNE X14, X9, cmp
ADD $1, X10
ADD $1, X12
SUB $1, X5
@@ -209,15 +209,15 @@
cmp8b:
MOV $0xff, X19
cmp8_loop:
- AND X17, X19, X8
+ AND X17, X19, X14
AND X18, X19, X9
- BNE X8, X9, cmp
+ BNE X14, X9, cmp
SLLI $8, X19
JMP cmp8_loop
cmp1a:
- SLTU X9, X8, X5
- SLTU X8, X9, X6
+ SLTU X9, X14, X5
+ SLTU X14, X9, X6
JMP cmp_ret
cmp1b:
SLTU X16, X15, X5
@@ -249,11 +249,11 @@
JMP cmp_ret
cmp_len:
- MOV X11, X8
+ MOV X11, X14
MOV X13, X9
cmp:
- SLTU X9, X8, X5
- SLTU X8, X9, X6
+ SLTU X9, X14, X5
+ SLTU X14, X9, X6
cmp_ret:
SUB X5, X6, X10
RET
diff --git a/src/math/big/arith_riscv64.s b/src/math/big/arith_riscv64.s
index 8817b1c..9289f9a 100644
--- a/src/math/big/arith_riscv64.s
+++ b/src/math/big/arith_riscv64.s
@@ -13,46 +13,41 @@
MOV z_len+8(FP), X5
MOV x_base+24(FP), X6
MOV y_base+48(FP), X7
- MOV z_base+0(FP), X8
+ MOV z_base+0(FP), X9
// compute unrolled loop lengths
- AND $3, X5, X9
+ AND $3, X5, X10
SRL $2, X5
XOR X28, X28 // clear carry
loop1:
- BEQZ X9, loop1done
+ BEQZ X10, loop1done
loop1cont:
// unroll 1X
- MOV 0(X6), X10
- MOV 0(X7), X11
- ADD X11, X10 // ADCS X11, X10, X10 (cr=X28)
- SLTU X11, X10, X31 // ...
- ADD X28, X10 // ...
- SLTU X28, X10, X28 // ...
+ MOV 0(X6), X11
+ MOV 0(X7), X12
+ ADD X12, X11 // ADCS X12, X11, X11 (cr=X28)
+ SLTU X12, X11, X31 // ...
+ ADD X28, X11 // ...
+ SLTU X28, X11, X28 // ...
ADD X31, X28 // ...
- MOV X10, 0(X8)
+ MOV X11, 0(X9)
ADD $8, X6
ADD $8, X7
- ADD $8, X8
- SUB $1, X9
- BNEZ X9, loop1cont
+ ADD $8, X9
+ SUB $1, X10
+ BNEZ X10, loop1cont
loop1done:
loop4:
BEQZ X5, loop4done
loop4cont:
// unroll 4X
- MOV 0(X6), X9
- MOV 8(X6), X10
- MOV 16(X6), X11
- MOV 24(X6), X12
- MOV 0(X7), X13
- MOV 8(X7), X14
- MOV 16(X7), X15
- MOV 24(X7), X16
- ADD X13, X9 // ADCS X13, X9, X9 (cr=X28)
- SLTU X13, X9, X31 // ...
- ADD X28, X9 // ...
- SLTU X28, X9, X28 // ...
- ADD X31, X28 // ...
+ MOV 0(X6), X10
+ MOV 8(X6), X11
+ MOV 16(X6), X12
+ MOV 24(X6), X13
+ MOV 0(X7), X14
+ MOV 8(X7), X15
+ MOV 16(X7), X16
+ MOV 24(X7), X17
ADD X14, X10 // ADCS X14, X10, X10 (cr=X28)
SLTU X14, X10, X31 // ...
ADD X28, X10 // ...
@@ -68,13 +63,18 @@
ADD X28, X12 // ...
SLTU X28, X12, X28 // ...
ADD X31, X28 // ...
- MOV X9, 0(X8)
- MOV X10, 8(X8)
- MOV X11, 16(X8)
- MOV X12, 24(X8)
+ ADD X17, X13 // ADCS X17, X13, X13 (cr=X28)
+ SLTU X17, X13, X31 // ...
+ ADD X28, X13 // ...
+ SLTU X28, X13, X28 // ...
+ ADD X31, X28 // ...
+ MOV X10, 0(X9)
+ MOV X11, 8(X9)
+ MOV X12, 16(X9)
+ MOV X13, 24(X9)
ADD $32, X6
ADD $32, X7
- ADD $32, X8
+ ADD $32, X9
SUB $1, X5
BNEZ X5, loop4cont
loop4done:
@@ -86,46 +86,41 @@
MOV z_len+8(FP), X5
MOV x_base+24(FP), X6
MOV y_base+48(FP), X7
- MOV z_base+0(FP), X8
+ MOV z_base+0(FP), X9
// compute unrolled loop lengths
- AND $3, X5, X9
+ AND $3, X5, X10
SRL $2, X5
XOR X28, X28 // clear carry
loop1:
- BEQZ X9, loop1done
+ BEQZ X10, loop1done
loop1cont:
// unroll 1X
- MOV 0(X6), X10
- MOV 0(X7), X11
- SLTU X28, X10, X31 // SBCS X11, X10, X10
- SUB X28, X10 // ...
- SLTU X11, X10, X28 // ...
- SUB X11, X10 // ...
+ MOV 0(X6), X11
+ MOV 0(X7), X12
+ SLTU X28, X11, X31 // SBCS X12, X11, X11
+ SUB X28, X11 // ...
+ SLTU X12, X11, X28 // ...
+ SUB X12, X11 // ...
ADD X31, X28 // ...
- MOV X10, 0(X8)
+ MOV X11, 0(X9)
ADD $8, X6
ADD $8, X7
- ADD $8, X8
- SUB $1, X9
- BNEZ X9, loop1cont
+ ADD $8, X9
+ SUB $1, X10
+ BNEZ X10, loop1cont
loop1done:
loop4:
BEQZ X5, loop4done
loop4cont:
// unroll 4X
- MOV 0(X6), X9
- MOV 8(X6), X10
- MOV 16(X6), X11
- MOV 24(X6), X12
- MOV 0(X7), X13
- MOV 8(X7), X14
- MOV 16(X7), X15
- MOV 24(X7), X16
- SLTU X28, X9, X31 // SBCS X13, X9, X9
- SUB X28, X9 // ...
- SLTU X13, X9, X28 // ...
- SUB X13, X9 // ...
- ADD X31, X28 // ...
+ MOV 0(X6), X10
+ MOV 8(X6), X11
+ MOV 16(X6), X12
+ MOV 24(X6), X13
+ MOV 0(X7), X14
+ MOV 8(X7), X15
+ MOV 16(X7), X16
+ MOV 24(X7), X17
SLTU X28, X10, X31 // SBCS X14, X10, X10
SUB X28, X10 // ...
SLTU X14, X10, X28 // ...
@@ -141,13 +136,18 @@
SLTU X16, X12, X28 // ...
SUB X16, X12 // ...
ADD X31, X28 // ...
- MOV X9, 0(X8)
- MOV X10, 8(X8)
- MOV X11, 16(X8)
- MOV X12, 24(X8)
+ SLTU X28, X13, X31 // SBCS X17, X13, X13
+ SUB X28, X13 // ...
+ SLTU X17, X13, X28 // ...
+ SUB X17, X13 // ...
+ ADD X31, X28 // ...
+ MOV X10, 0(X9)
+ MOV X11, 8(X9)
+ MOV X12, 16(X9)
+ MOV X13, 24(X9)
ADD $32, X6
ADD $32, X7
- ADD $32, X8
+ ADD $32, X9
SUB $1, X5
BNEZ X5, loop4cont
loop4done:
@@ -160,69 +160,69 @@
BEQZ X5, ret0
MOV s+48(FP), X6
MOV x_base+24(FP), X7
- MOV z_base+0(FP), X8
+ MOV z_base+0(FP), X9
// run loop backward
- SLL $3, X5, X9
- ADD X9, X7
- SLL $3, X5, X9
- ADD X9, X8
+ SLL $3, X5, X10
+ ADD X10, X7
+ SLL $3, X5, X10
+ ADD X10, X9
// shift first word into carry
- MOV -8(X7), X9
- MOV $64, X10
- SUB X6, X10
- SRL X10, X9, X11
- SLL X6, X9
- MOV X11, c+56(FP)
+ MOV -8(X7), X10
+ MOV $64, X11
+ SUB X6, X11
+ SRL X11, X10, X12
+ SLL X6, X10
+ MOV X12, c+56(FP)
// shift remaining words
SUB $1, X5
// compute unrolled loop lengths
- AND $3, X5, X11
+ AND $3, X5, X12
SRL $2, X5
loop1:
- BEQZ X11, loop1done
+ BEQZ X12, loop1done
loop1cont:
// unroll 1X
- MOV -16(X7), X12
- SRL X10, X12, X13
- OR X9, X13
- SLL X6, X12, X9
- MOV X13, -8(X8)
+ MOV -16(X7), X13
+ SRL X11, X13, X14
+ OR X10, X14
+ SLL X6, X13, X10
+ MOV X14, -8(X9)
ADD $-8, X7
- ADD $-8, X8
- SUB $1, X11
- BNEZ X11, loop1cont
+ ADD $-8, X9
+ SUB $1, X12
+ BNEZ X12, loop1cont
loop1done:
loop4:
BEQZ X5, loop4done
loop4cont:
// unroll 4X
- MOV -16(X7), X11
- MOV -24(X7), X12
- MOV -32(X7), X13
- MOV -40(X7), X14
- SRL X10, X11, X15
- OR X9, X15
- SLL X6, X11, X9
- SRL X10, X12, X11
- OR X9, X11
- SLL X6, X12, X9
- SRL X10, X13, X12
- OR X9, X12
- SLL X6, X13, X9
- SRL X10, X14, X13
- OR X9, X13
- SLL X6, X14, X9
- MOV X15, -8(X8)
- MOV X11, -16(X8)
- MOV X12, -24(X8)
- MOV X13, -32(X8)
+ MOV -16(X7), X12
+ MOV -24(X7), X13
+ MOV -32(X7), X14
+ MOV -40(X7), X15
+ SRL X11, X12, X16
+ OR X10, X16
+ SLL X6, X12, X10
+ SRL X11, X13, X12
+ OR X10, X12
+ SLL X6, X13, X10
+ SRL X11, X14, X13
+ OR X10, X13
+ SLL X6, X14, X10
+ SRL X11, X15, X14
+ OR X10, X14
+ SLL X6, X15, X10
+ MOV X16, -8(X9)
+ MOV X12, -16(X9)
+ MOV X13, -24(X9)
+ MOV X14, -32(X9)
ADD $-32, X7
- ADD $-32, X8
+ ADD $-32, X9
SUB $1, X5
BNEZ X5, loop4cont
loop4done:
// store final shifted bits
- MOV X9, -8(X8)
+ MOV X10, -8(X9)
RET
ret0:
MOV X0, c+56(FP)
@@ -234,64 +234,64 @@
BEQZ X5, ret0
MOV s+48(FP), X6
MOV x_base+24(FP), X7
- MOV z_base+0(FP), X8
+ MOV z_base+0(FP), X9
// shift first word into carry
- MOV 0(X7), X9
- MOV $64, X10
- SUB X6, X10
- SLL X10, X9, X11
- SRL X6, X9
- MOV X11, c+56(FP)
+ MOV 0(X7), X10
+ MOV $64, X11
+ SUB X6, X11
+ SLL X11, X10, X12
+ SRL X6, X10
+ MOV X12, c+56(FP)
// shift remaining words
SUB $1, X5
// compute unrolled loop lengths
- AND $3, X5, X11
+ AND $3, X5, X12
SRL $2, X5
loop1:
- BEQZ X11, loop1done
+ BEQZ X12, loop1done
loop1cont:
// unroll 1X
- MOV 8(X7), X12
- SLL X10, X12, X13
- OR X9, X13
- SRL X6, X12, X9
- MOV X13, 0(X8)
+ MOV 8(X7), X13
+ SLL X11, X13, X14
+ OR X10, X14
+ SRL X6, X13, X10
+ MOV X14, 0(X9)
ADD $8, X7
- ADD $8, X8
- SUB $1, X11
- BNEZ X11, loop1cont
+ ADD $8, X9
+ SUB $1, X12
+ BNEZ X12, loop1cont
loop1done:
loop4:
BEQZ X5, loop4done
loop4cont:
// unroll 4X
- MOV 8(X7), X11
- MOV 16(X7), X12
- MOV 24(X7), X13
- MOV 32(X7), X14
- SLL X10, X11, X15
- OR X9, X15
- SRL X6, X11, X9
- SLL X10, X12, X11
- OR X9, X11
- SRL X6, X12, X9
- SLL X10, X13, X12
- OR X9, X12
- SRL X6, X13, X9
- SLL X10, X14, X13
- OR X9, X13
- SRL X6, X14, X9
- MOV X15, 0(X8)
- MOV X11, 8(X8)
- MOV X12, 16(X8)
- MOV X13, 24(X8)
+ MOV 8(X7), X12
+ MOV 16(X7), X13
+ MOV 24(X7), X14
+ MOV 32(X7), X15
+ SLL X11, X12, X16
+ OR X10, X16
+ SRL X6, X12, X10
+ SLL X11, X13, X12
+ OR X10, X12
+ SRL X6, X13, X10
+ SLL X11, X14, X13
+ OR X10, X13
+ SRL X6, X14, X10
+ SLL X11, X15, X14
+ OR X10, X14
+ SRL X6, X15, X10
+ MOV X16, 0(X9)
+ MOV X12, 8(X9)
+ MOV X13, 16(X9)
+ MOV X14, 24(X9)
ADD $32, X7
- ADD $32, X8
+ ADD $32, X9
SUB $1, X5
BNEZ X5, loop4cont
loop4done:
// store final shifted bits
- MOV X9, 0(X8)
+ MOV X10, 0(X9)
RET
ret0:
MOV X0, c+56(FP)
@@ -302,63 +302,63 @@
MOV m+48(FP), X5
MOV a+56(FP), X6
MOV z_len+8(FP), X7
- MOV x_base+24(FP), X8
- MOV z_base+0(FP), X9
+ MOV x_base+24(FP), X9
+ MOV z_base+0(FP), X10
// compute unrolled loop lengths
- AND $3, X7, X10
+ AND $3, X7, X11
SRL $2, X7
loop1:
- BEQZ X10, loop1done
+ BEQZ X11, loop1done
loop1cont:
// unroll 1X
- MOV 0(X8), X11
+ MOV 0(X9), X12
// synthetic carry, one column at a time
- MUL X5, X11, X12
- MULHU X5, X11, X13
- ADD X6, X12, X11 // ADDS X6, X12, X11 (cr=X28)
- SLTU X6, X11, X28 // ...
- ADD X28, X13, X6 // ADC $0, X13, X6
- MOV X11, 0(X9)
- ADD $8, X8
+ MUL X5, X12, X13
+ MULHU X5, X12, X14
+ ADD X6, X13, X12 // ADDS X6, X13, X12 (cr=X28)
+ SLTU X6, X12, X28 // ...
+ ADD X28, X14, X6 // ADC $0, X14, X6
+ MOV X12, 0(X10)
ADD $8, X9
- SUB $1, X10
- BNEZ X10, loop1cont
+ ADD $8, X10
+ SUB $1, X11
+ BNEZ X11, loop1cont
loop1done:
loop4:
BEQZ X7, loop4done
loop4cont:
// unroll 4X
- MOV 0(X8), X10
- MOV 8(X8), X11
- MOV 16(X8), X12
- MOV 24(X8), X13
+ MOV 0(X9), X11
+ MOV 8(X9), X12
+ MOV 16(X9), X13
+ MOV 24(X9), X14
// synthetic carry, one column at a time
- MUL X5, X10, X14
- MULHU X5, X10, X15
- ADD X6, X14, X10 // ADDS X6, X14, X10 (cr=X28)
- SLTU X6, X10, X28 // ...
- ADD X28, X15, X6 // ADC $0, X15, X6
- MUL X5, X11, X14
- MULHU X5, X11, X15
- ADD X6, X14, X11 // ADDS X6, X14, X11 (cr=X28)
+ MUL X5, X11, X15
+ MULHU X5, X11, X16
+ ADD X6, X15, X11 // ADDS X6, X15, X11 (cr=X28)
SLTU X6, X11, X28 // ...
- ADD X28, X15, X6 // ADC $0, X15, X6
- MUL X5, X12, X14
- MULHU X5, X12, X15
- ADD X6, X14, X12 // ADDS X6, X14, X12 (cr=X28)
+ ADD X28, X16, X6 // ADC $0, X16, X6
+ MUL X5, X12, X15
+ MULHU X5, X12, X16
+ ADD X6, X15, X12 // ADDS X6, X15, X12 (cr=X28)
SLTU X6, X12, X28 // ...
- ADD X28, X15, X6 // ADC $0, X15, X6
- MUL X5, X13, X14
- MULHU X5, X13, X15
- ADD X6, X14, X13 // ADDS X6, X14, X13 (cr=X28)
+ ADD X28, X16, X6 // ADC $0, X16, X6
+ MUL X5, X13, X15
+ MULHU X5, X13, X16
+ ADD X6, X15, X13 // ADDS X6, X15, X13 (cr=X28)
SLTU X6, X13, X28 // ...
- ADD X28, X15, X6 // ADC $0, X15, X6
- MOV X10, 0(X9)
- MOV X11, 8(X9)
- MOV X12, 16(X9)
- MOV X13, 24(X9)
- ADD $32, X8
+ ADD X28, X16, X6 // ADC $0, X16, X6
+ MUL X5, X14, X15
+ MULHU X5, X14, X16
+ ADD X6, X15, X14 // ADDS X6, X15, X14 (cr=X28)
+ SLTU X6, X14, X28 // ...
+ ADD X28, X16, X6 // ADC $0, X16, X6
+ MOV X11, 0(X10)
+ MOV X12, 8(X10)
+ MOV X13, 16(X10)
+ MOV X14, 24(X10)
ADD $32, X9
+ ADD $32, X10
SUB $1, X7
BNEZ X7, loop4cont
loop4done:
@@ -370,86 +370,86 @@
MOV m+72(FP), X5
MOV a+80(FP), X6
MOV z_len+8(FP), X7
- MOV x_base+24(FP), X8
- MOV y_base+48(FP), X9
- MOV z_base+0(FP), X10
+ MOV x_base+24(FP), X9
+ MOV y_base+48(FP), X10
+ MOV z_base+0(FP), X11
// compute unrolled loop lengths
- AND $3, X7, X11
+ AND $3, X7, X12
SRL $2, X7
loop1:
- BEQZ X11, loop1done
+ BEQZ X12, loop1done
loop1cont:
// unroll 1X
- MOV 0(X8), X12
MOV 0(X9), X13
+ MOV 0(X10), X14
// synthetic carry, one column at a time
- MUL X5, X13, X14
- MULHU X5, X13, X15
- ADD X12, X14 // ADDS X12, X14, X14 (cr=X28)
- SLTU X12, X14, X28 // ...
- ADD X28, X15 // ADC $0, X15, X15
- ADD X6, X14, X13 // ADDS X6, X14, X13 (cr=X28)
- SLTU X6, X13, X28 // ...
- ADD X28, X15, X6 // ADC $0, X15, X6
- MOV X13, 0(X10)
- ADD $8, X8
+ MUL X5, X14, X15
+ MULHU X5, X14, X16
+ ADD X13, X15 // ADDS X13, X15, X15 (cr=X28)
+ SLTU X13, X15, X28 // ...
+ ADD X28, X16 // ADC $0, X16, X16
+ ADD X6, X15, X14 // ADDS X6, X15, X14 (cr=X28)
+ SLTU X6, X14, X28 // ...
+ ADD X28, X16, X6 // ADC $0, X16, X6
+ MOV X14, 0(X11)
ADD $8, X9
ADD $8, X10
- SUB $1, X11
- BNEZ X11, loop1cont
+ ADD $8, X11
+ SUB $1, X12
+ BNEZ X12, loop1cont
loop1done:
loop4:
BEQZ X7, loop4done
loop4cont:
// unroll 4X
- MOV 0(X8), X11
- MOV 8(X8), X12
- MOV 16(X8), X13
- MOV 24(X8), X14
- MOV 0(X9), X15
- MOV 8(X9), X16
- MOV 16(X9), X17
- MOV 24(X9), X18
+ MOV 0(X9), X12
+ MOV 8(X9), X13
+ MOV 16(X9), X14
+ MOV 24(X9), X15
+ MOV 0(X10), X16
+ MOV 8(X10), X17
+ MOV 16(X10), X18
+ MOV 24(X10), X19
// synthetic carry, one column at a time
- MUL X5, X15, X19
- MULHU X5, X15, X20
- ADD X11, X19 // ADDS X11, X19, X19 (cr=X28)
- SLTU X11, X19, X28 // ...
- ADD X28, X20 // ADC $0, X20, X20
- ADD X6, X19, X15 // ADDS X6, X19, X15 (cr=X28)
- SLTU X6, X15, X28 // ...
- ADD X28, X20, X6 // ADC $0, X20, X6
- MUL X5, X16, X19
- MULHU X5, X16, X20
- ADD X12, X19 // ADDS X12, X19, X19 (cr=X28)
- SLTU X12, X19, X28 // ...
- ADD X28, X20 // ADC $0, X20, X20
- ADD X6, X19, X16 // ADDS X6, X19, X16 (cr=X28)
+ MUL X5, X16, X20
+ MULHU X5, X16, X21
+ ADD X12, X20 // ADDS X12, X20, X20 (cr=X28)
+ SLTU X12, X20, X28 // ...
+ ADD X28, X21 // ADC $0, X21, X21
+ ADD X6, X20, X16 // ADDS X6, X20, X16 (cr=X28)
SLTU X6, X16, X28 // ...
- ADD X28, X20, X6 // ADC $0, X20, X6
- MUL X5, X17, X19
- MULHU X5, X17, X20
- ADD X13, X19 // ADDS X13, X19, X19 (cr=X28)
- SLTU X13, X19, X28 // ...
- ADD X28, X20 // ADC $0, X20, X20
- ADD X6, X19, X17 // ADDS X6, X19, X17 (cr=X28)
+ ADD X28, X21, X6 // ADC $0, X21, X6
+ MUL X5, X17, X20
+ MULHU X5, X17, X21
+ ADD X13, X20 // ADDS X13, X20, X20 (cr=X28)
+ SLTU X13, X20, X28 // ...
+ ADD X28, X21 // ADC $0, X21, X21
+ ADD X6, X20, X17 // ADDS X6, X20, X17 (cr=X28)
SLTU X6, X17, X28 // ...
- ADD X28, X20, X6 // ADC $0, X20, X6
- MUL X5, X18, X19
- MULHU X5, X18, X20
- ADD X14, X19 // ADDS X14, X19, X19 (cr=X28)
- SLTU X14, X19, X28 // ...
- ADD X28, X20 // ADC $0, X20, X20
- ADD X6, X19, X18 // ADDS X6, X19, X18 (cr=X28)
+ ADD X28, X21, X6 // ADC $0, X21, X6
+ MUL X5, X18, X20
+ MULHU X5, X18, X21
+ ADD X14, X20 // ADDS X14, X20, X20 (cr=X28)
+ SLTU X14, X20, X28 // ...
+ ADD X28, X21 // ADC $0, X21, X21
+ ADD X6, X20, X18 // ADDS X6, X20, X18 (cr=X28)
SLTU X6, X18, X28 // ...
- ADD X28, X20, X6 // ADC $0, X20, X6
- MOV X15, 0(X10)
- MOV X16, 8(X10)
- MOV X17, 16(X10)
- MOV X18, 24(X10)
- ADD $32, X8
+ ADD X28, X21, X6 // ADC $0, X21, X6
+ MUL X5, X19, X20
+ MULHU X5, X19, X21
+ ADD X15, X20 // ADDS X15, X20, X20 (cr=X28)
+ SLTU X15, X20, X28 // ...
+ ADD X28, X21 // ADC $0, X21, X21
+ ADD X6, X20, X19 // ADDS X6, X20, X19 (cr=X28)
+ SLTU X6, X19, X28 // ...
+ ADD X28, X21, X6 // ADC $0, X21, X6
+ MOV X16, 0(X11)
+ MOV X17, 8(X11)
+ MOV X18, 16(X11)
+ MOV X19, 24(X11)
ADD $32, X9
ADD $32, X10
+ ADD $32, X11
SUB $1, X7
BNEZ X7, loop4cont
loop4done:
diff --git a/src/math/big/internal/asmgen/riscv64.go b/src/math/big/internal/asmgen/riscv64.go
index 8995c4c..20600d4 100644
--- a/src/math/big/internal/asmgen/riscv64.go
+++ b/src/math/big/internal/asmgen/riscv64.go
@@ -16,10 +16,11 @@
// X2 is SP.
// X3 is SB.
// X4 is TP.
+ // X8 is FP.
// X27 is g.
// X28 and X29 are our virtual carry flags.
// X31 is the assembler/linker temporary (which we use too).
- "X5", "X6", "X7", "X8", "X9",
+ "X5", "X6", "X7", "X9",
"X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19",
"X20", "X21", "X22", "X23", "X24", "X25", "X26",
"X30",
diff --git a/src/runtime/asan_riscv64.s b/src/runtime/asan_riscv64.s
index 5a33336..94b05b2 100644
--- a/src/runtime/asan_riscv64.s
+++ b/src/runtime/asan_riscv64.s
@@ -76,7 +76,7 @@
// Switches SP to g0 stack and calls (X14). Arguments already set.
TEXT asancall<>(SB), NOSPLIT, $0-0
- MOV X2, X8 // callee-saved
+ MOV X2, X9 // callee-saved
BEQZ g, call // no g, still on a system stack
MOV g_m(g), X21
@@ -91,5 +91,5 @@
call:
JALR RA, X14
- MOV X8, X2
+ MOV X9, X2
RET
diff --git a/src/runtime/asm_riscv64.s b/src/runtime/asm_riscv64.s
index b599989..a206ee4 100644
--- a/src/runtime/asm_riscv64.s
+++ b/src/runtime/asm_riscv64.s
@@ -64,10 +64,13 @@
// func rt0_go()
TEXT runtime·rt0_go(SB),NOSPLIT|TOPFRAME,$0
// X2 = stack; A0 = argc; A1 = argv
- SUB $24, X2
+ SUB $32, X2
MOV A0, 8(X2) // argc
MOV A1, 16(X2) // argv
+ // Call stack unwinding must not proceed past this frame.
+ MOV ZERO, X8
+
// create istack out of the given (operating system) stack.
// _cgo_init may update stackguard.
MOV $runtime·g0(SB), g
@@ -125,6 +128,8 @@
RET
TEXT runtime·mstart(SB),NOSPLIT|TOPFRAME,$0
+ // Call stack unwinding must not proceed past this frame.
+ MOV ZERO, X8
CALL runtime·mstart0(SB)
RET // not reached
@@ -181,6 +186,7 @@
CALL runtime·save_g(SB)
MOV (g_sched+gobuf_sp)(g), T0
MOV T0, X2
+ MOV (g_sched+gobuf_bp)(g), X8
// call target function
MOV 0(CTXT), T1 // code pointer
@@ -192,6 +198,8 @@
CALL runtime·save_g(SB)
MOV (g_sched+gobuf_sp)(g), X2
MOV ZERO, (g_sched+gobuf_sp)(g)
+ MOV (g_sched+gobuf_bp)(g), X8
+ MOV ZERO, (g_sched+gobuf_bp)(g)
RET
noswitch:
@@ -199,7 +207,8 @@
// Using a tail call here cleans up tracebacks since we won't stop
// at an intermediate systemstack.
MOV 0(CTXT), T1 // code pointer
- ADD $8, X2
+ MOV -8(X2), X8
+ ADD $16, X2
JMP (T1)
// func switchToCrashStack0(fn func())
@@ -247,6 +256,7 @@
MOV T0, (g_sched+gobuf_pc)(g)
MOV RA, (g_sched+gobuf_lr)(g)
MOV CTXT, (g_sched+gobuf_ctxt)(g)
+ MOV X8, (g_sched+gobuf_bp)(g)
// Cannot grow scheduler stack (m->g0).
MOV g_m(g), A0
@@ -265,12 +275,14 @@
// Set m->morebuf to f's caller.
MOV RA, (m_morebuf+gobuf_pc)(A0) // f's caller's PC
MOV X2, (m_morebuf+gobuf_sp)(A0) // f's caller's SP
+ MOV X8, (m_morebuf+gobuf_bp)(A0) // f's caller's FP
MOV g, (m_morebuf+gobuf_g)(A0)
// Call newstack on m->g0's stack.
MOV m_g0(A0), g
CALL runtime·save_g(SB)
MOV (g_sched+gobuf_sp)(g), X2
+ MOV ZERO, X8
// Create a stack frame on g0 to call newstack.
MOV ZERO, -8(X2) // Zero saved LR in frame
SUB $8, X2
@@ -316,9 +328,11 @@
CALL runtime·save_g(SB)
MOV gobuf_sp(T0), X2
+ MOV gobuf_bp(T0), X8
MOV gobuf_lr(T0), RA
MOV gobuf_ctxt(T0), CTXT
MOV ZERO, gobuf_sp(T0)
+ MOV ZERO, gobuf_bp(T0)
MOV ZERO, gobuf_lr(T0)
MOV ZERO, gobuf_ctxt(T0)
MOV gobuf_pc(T0), T0
@@ -340,6 +354,7 @@
MOV X2, (g_sched+gobuf_sp)(g)
MOV RA, (g_sched+gobuf_pc)(g)
MOV ZERO, (g_sched+gobuf_lr)(g)
+ MOV X8, (g_sched+gobuf_bp)(g)
// Switch to m->g0 & its stack, call fn.
MOV g, X10
@@ -350,6 +365,7 @@
JMP runtime·badmcall(SB)
MOV 0(CTXT), T1 // code pointer
MOV (g_sched+gobuf_sp)(g), X2 // sp = m->g0->sched.sp
+ MOV ZERO, X8
// we don't need special macro for regabi since arg0(X10) = g
SUB $16, X2
MOV X10, 8(X2) // setup g
@@ -364,10 +380,11 @@
// Smashes X31.
TEXT gosave_systemstack_switch<>(SB),NOSPLIT|NOFRAME,$0
MOV $runtime·systemstack_switch(SB), X31
- ADD $8, X31 // get past prologue
+ ADD $24, X31 // get past prologue
MOV X31, (g_sched+gobuf_pc)(g)
MOV X2, (g_sched+gobuf_sp)(g)
MOV ZERO, (g_sched+gobuf_lr)(g)
+ MOV X8, (g_sched+gobuf_bp)(g)
// Assert ctxt is zero. See func save.
MOV (g_sched+gobuf_ctxt)(g), X31
BEQ ZERO, X31, 2(PC)
@@ -380,7 +397,9 @@
TEXT ·asmcgocall_no_g(SB),NOSPLIT,$0-16
MOV fn+0(FP), X11
MOV arg+8(FP), X10
+ SUB $16, X2
JALR RA, (X11)
+ ADD $16, X2
RET
// func asmcgocall(fn, arg unsafe.Pointer) int32
@@ -391,8 +410,8 @@
MOV fn+0(FP), X11
MOV arg+8(FP), X10
- MOV X2, X8 // save original stack pointer
- MOV g, X9
+ MOV X2, X9 // save original stack pointer
+ MOV g, X18
// Figure out if we need to switch to m->g0 stack.
// We get called to create new OS threads too, and those
@@ -408,15 +427,16 @@
MOV X7, g
CALL runtime·save_g(SB)
MOV (g_sched+gobuf_sp)(g), X2
+ MOV (g_sched+gobuf_bp)(g), X8
// Now on a scheduling stack (a pthread-created stack).
g0:
// Save room for two of our pointers.
SUB $16, X2
- MOV X9, 0(X2) // save old g on stack
- MOV (g_stack+stack_hi)(X9), X9
- SUB X8, X9, X8
- MOV X8, 8(X2) // save depth in old g stack (can't just save SP, as stack might be copied during a callback)
+ MOV X18, 0(X2) // save old g on stack
+ MOV (g_stack+stack_hi)(X18), X5
+ SUB X9, X5, X6
+ MOV X6, 8(X2) // save depth in old g stack (can't just save SP, as stack might be copied during a callback)
JALR RA, (X11)
@@ -648,6 +668,7 @@
MOV g_m(g), X5
MOV m_g0(X5), X6
MOV X2, (g_sched+gobuf_sp)(X6)
+ MOV X8, (g_sched+gobuf_bp)(X6)
havem:
// Now there's a valid m, and we're running on its m->g0.
@@ -659,6 +680,7 @@
MOV (g_sched+gobuf_sp)(X6), X7
MOV X7, savedsp-24(SP) // must match frame size
MOV X2, (g_sched+gobuf_sp)(X6)
+ MOV X8, (g_sched+gobuf_bp)(X6)
// Switch to m->curg stack and call runtime.cgocallbackg.
// Because we are taking over the execution of m->curg
@@ -675,21 +697,24 @@
CALL runtime·save_g(SB)
MOV (g_sched+gobuf_sp)(g), X6 // prepare stack as X6
MOV (g_sched+gobuf_pc)(g), X7
- MOV X7, -(24+8)(X6) // "saved LR"; must match frame size
+ MOV X7, -(24+16)(X6) // "saved LR"; must match frame size
+ // Preserve m->curg->sched.bp in the frame-pointer link slot (one word below the SP).
+ MOV (g_sched+gobuf_bp)(g), X11
+ MOV X11, -(24+24)(X6)
// Gather our arguments into registers.
MOV fn+0(FP), X7
- MOV frame+8(FP), X8
+ MOV frame+8(FP), X12
MOV ctxt+16(FP), X9
- MOV $-(24+8)(X6), X2 // switch stack; must match frame size
+ MOV $-(24+16)(X6), X2 // switch stack; must match frame size
MOV X7, 8(X2)
- MOV X8, 16(X2)
+ MOV X12, 16(X2)
MOV X9, 24(X2)
CALL runtime·cgocallbackg(SB)
// Restore g->sched (== m->curg->sched) from saved values.
MOV 0(X2), X7
MOV X7, (g_sched+gobuf_pc)(g)
- MOV $(24+8)(X2), X6 // must match frame size
+ MOV $(24+16)(X2), X6 // must match frame size
MOV X6, (g_sched+gobuf_sp)(g)
// Switch back to m->g0's stack and restore m->g0->sched.sp.
@@ -757,30 +782,29 @@
MOV X15, (5*8)(X25)
MOV X16, (6*8)(X25)
MOV X17, (7*8)(X25)
- MOV X8, (8*8)(X25)
- MOV X9, (9*8)(X25)
- MOV X18, (10*8)(X25)
- MOV X19, (11*8)(X25)
- MOV X20, (12*8)(X25)
- MOV X21, (13*8)(X25)
- MOV X22, (14*8)(X25)
- MOV X23, (15*8)(X25)
- MOVD F10, (16*8)(X25)
- MOVD F11, (17*8)(X25)
- MOVD F12, (18*8)(X25)
- MOVD F13, (19*8)(X25)
- MOVD F14, (20*8)(X25)
- MOVD F15, (21*8)(X25)
- MOVD F16, (22*8)(X25)
- MOVD F17, (23*8)(X25)
- MOVD F8, (24*8)(X25)
- MOVD F9, (25*8)(X25)
- MOVD F18, (26*8)(X25)
- MOVD F19, (27*8)(X25)
- MOVD F20, (28*8)(X25)
- MOVD F21, (29*8)(X25)
- MOVD F22, (30*8)(X25)
- MOVD F23, (31*8)(X25)
+ MOV X9, (8*8)(X25)
+ MOV X18, (9*8)(X25)
+ MOV X19, (10*8)(X25)
+ MOV X20, (11*8)(X25)
+ MOV X21, (12*8)(X25)
+ MOV X22, (13*8)(X25)
+ MOV X23, (14*8)(X25)
+ MOVD F10, (15*8)(X25)
+ MOVD F11, (16*8)(X25)
+ MOVD F12, (17*8)(X25)
+ MOVD F13, (18*8)(X25)
+ MOVD F14, (19*8)(X25)
+ MOVD F15, (20*8)(X25)
+ MOVD F16, (21*8)(X25)
+ MOVD F17, (22*8)(X25)
+ MOVD F8, (23*8)(X25)
+ MOVD F9, (24*8)(X25)
+ MOVD F18, (25*8)(X25)
+ MOVD F19, (26*8)(X25)
+ MOVD F20, (27*8)(X25)
+ MOVD F21, (28*8)(X25)
+ MOVD F22, (29*8)(X25)
+ MOVD F23, (30*8)(X25)
RET
// unspillArgs loads args into registers from a *internal/abi.RegArgs in X25.
@@ -793,30 +817,33 @@
MOV (5*8)(X25), X15
MOV (6*8)(X25), X16
MOV (7*8)(X25), X17
- MOV (8*8)(X25), X8
- MOV (9*8)(X25), X9
- MOV (10*8)(X25), X18
- MOV (11*8)(X25), X19
- MOV (12*8)(X25), X20
- MOV (13*8)(X25), X21
- MOV (14*8)(X25), X22
- MOV (15*8)(X25), X23
- MOVD (16*8)(X25), F10
- MOVD (17*8)(X25), F11
- MOVD (18*8)(X25), F12
- MOVD (19*8)(X25), F13
- MOVD (20*8)(X25), F14
- MOVD (21*8)(X25), F15
- MOVD (22*8)(X25), F16
- MOVD (23*8)(X25), F17
- MOVD (24*8)(X25), F8
- MOVD (25*8)(X25), F9
- MOVD (26*8)(X25), F18
- MOVD (27*8)(X25), F19
- MOVD (28*8)(X25), F20
- MOVD (29*8)(X25), F21
- MOVD (30*8)(X25), F22
- MOVD (31*8)(X25), F23
+ MOV (8*8)(X25), X9
+ MOV (9*8)(X25), X18
+ MOV (10*8)(X25), X19
+ MOV (11*8)(X25), X20
+ MOV (12*8)(X25), X21
+ MOV (13*8)(X25), X22
+ MOV (14*8)(X25), X23
+ MOVD (15*8)(X25), F10
+ MOVD (16*8)(X25), F11
+ MOVD (17*8)(X25), F12
+ MOVD (18*8)(X25), F13
+ MOVD (19*8)(X25), F14
+ MOVD (20*8)(X25), F15
+ MOVD (21*8)(X25), F16
+ MOVD (22*8)(X25), F17
+ MOVD (23*8)(X25), F8
+ MOVD (24*8)(X25), F9
+ MOVD (25*8)(X25), F18
+ MOVD (26*8)(X25), F19
+ MOVD (27*8)(X25), F20
+ MOVD (28*8)(X25), F21
+ MOVD (29*8)(X25), F22
+ MOVD (30*8)(X25), F23
+ RET
+
+TEXT ·getfp<ABIInternal>(SB),NOSPLIT|NOFRAME,$0
+ MOV X8, X10
RET
// gcWriteBarrier informs the GC about heap pointer writes.
@@ -860,6 +887,7 @@
// X2 is SP
// X3 is GP
// X4 is TP
+ // X8 is FP
MOV X7, 3*8(X2)
MOV X8, 4*8(X2)
MOV X9, 5*8(X2)
diff --git a/src/runtime/cgo/asm_riscv64.s b/src/runtime/cgo/asm_riscv64.s
index d8be554..81513e9 100644
--- a/src/runtime/cgo/asm_riscv64.s
+++ b/src/runtime/cgo/asm_riscv64.s
@@ -11,8 +11,8 @@
// function.
TEXT ·set_crosscall2(SB),NOSPLIT,$0-0
MOV _crosscall2_ptr(SB), X7
- MOV $crosscall2_trampoline<>(SB), X8
- MOV X8, (X7)
+ MOV $crosscall2_trampoline<>(SB), X9
+ MOV X9, (X7)
RET
TEXT crosscall2_trampoline<>(SB),NOSPLIT,$0-0
diff --git a/src/runtime/mkpreempt.go b/src/runtime/mkpreempt.go
index ca1c6e4..b908672 100644
--- a/src/runtime/mkpreempt.go
+++ b/src/runtime/mkpreempt.go
@@ -901,12 +901,12 @@
func genRISCV64(g *gen) {
p := g.p
- // X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X27 (g), X31 (TMP) are special.
+ // X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X8(FP), X27 (g), X31 (TMP) are special.
var l = layout{sp: "X2", stack: 8}
// Add integer registers (X5-X26, X28-30).
for i := 5; i < 31; i++ {
- if i == 27 {
+ if i == 8 || i == 27 {
continue
}
reg := fmt.Sprintf("X%d", i)
@@ -919,14 +919,18 @@
l.add("MOVD", reg, 8)
}
+ l.stack += 8
p("MOV X1, -%d(X2)", l.stack)
p("SUB $%d, X2", l.stack)
+ p("MOV X8, -8(X2)")
+ p("ADD $8, X2, X8")
l.save(g)
p("CALL ·asyncPreempt2(SB)")
l.restore(g)
p("MOV %d(X2), X1", l.stack)
+ p("MOV -8(X2), X8")
p("MOV (X2), X31")
- p("ADD $%d, X2", l.stack+8)
+ p("ADD $%d, X2", l.stack+16)
p("JMP (X31)")
}
diff --git a/src/runtime/mprof.go b/src/runtime/mprof.go
index a4cfef7..4cdcb9e 100644
--- a/src/runtime/mprof.go
+++ b/src/runtime/mprof.go
@@ -589,7 +589,12 @@
}
for n < len(pcBuf) && fp != nil {
// return addr sits one word above the frame pointer
- pc := *(*uintptr)(unsafe.Pointer(uintptr(fp) + goarch.PtrSize))
+ var pc uintptr
+ if goarch.ArchFamily == goarch.RISCV64 {
+ pc = *(*uintptr)(unsafe.Pointer(uintptr(fp) - goarch.PtrSize))
+ } else {
+ pc = *(*uintptr)(unsafe.Pointer(uintptr(fp) + goarch.PtrSize))
+ }
if skip > 0 {
callPC := pc - 1
@@ -612,7 +617,11 @@
}
// follow the frame pointer to the next one
- fp = unsafe.Pointer(*(*uintptr)(fp))
+ if goarch.ArchFamily == goarch.RISCV64 {
+ fp = unsafe.Pointer(*(*uintptr)(unsafe.Pointer(uintptr(fp) - 2*goarch.PtrSize)))
+ } else {
+ fp = unsafe.Pointer(*(*uintptr)(fp))
+ }
}
return n
}
diff --git a/src/runtime/panic.go b/src/runtime/panic.go
index 1429279..2614995 100644
--- a/src/runtime/panic.go
+++ b/src/runtime/panic.go
@@ -1423,6 +1423,10 @@
// than the sp. fp is totally useless to us here, because it
// only gets us to the caller's fp.
gp.sched.bp = sp - goarch.PtrSize
+ case goarch.IsRiscv64 != 0:
+ // On riscv64 with frame pointers enabled, the architectural bp
+ // points one word higher than the sp.
+ gp.sched.bp = sp + goarch.PtrSize
}
gogo(&gp.sched)
}
@@ -1719,6 +1723,7 @@
}
// For debugging only.
+//
//go:noinline
//go:nosplit
func dumpPanicDeferState(where string, gp *g) {
diff --git a/src/runtime/preempt_riscv64.s b/src/runtime/preempt_riscv64.s
index bbb6447..1210bb7 100644
--- a/src/runtime/preempt_riscv64.s
+++ b/src/runtime/preempt_riscv64.s
@@ -6,122 +6,124 @@
TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
MOV X1, -464(X2)
SUB $464, X2
+ MOV X8, -8(X2)
+ ADD $8, X2, X8
MOV X5, 8(X2)
MOV X6, 16(X2)
MOV X7, 24(X2)
- MOV X8, 32(X2)
- MOV X9, 40(X2)
- MOV X10, 48(X2)
- MOV X11, 56(X2)
- MOV X12, 64(X2)
- MOV X13, 72(X2)
- MOV X14, 80(X2)
- MOV X15, 88(X2)
- MOV X16, 96(X2)
- MOV X17, 104(X2)
- MOV X18, 112(X2)
- MOV X19, 120(X2)
- MOV X20, 128(X2)
- MOV X21, 136(X2)
- MOV X22, 144(X2)
- MOV X23, 152(X2)
- MOV X24, 160(X2)
- MOV X25, 168(X2)
- MOV X26, 176(X2)
- MOV X28, 184(X2)
- MOV X29, 192(X2)
- MOV X30, 200(X2)
- MOVD F0, 208(X2)
- MOVD F1, 216(X2)
- MOVD F2, 224(X2)
- MOVD F3, 232(X2)
- MOVD F4, 240(X2)
- MOVD F5, 248(X2)
- MOVD F6, 256(X2)
- MOVD F7, 264(X2)
- MOVD F8, 272(X2)
- MOVD F9, 280(X2)
- MOVD F10, 288(X2)
- MOVD F11, 296(X2)
- MOVD F12, 304(X2)
- MOVD F13, 312(X2)
- MOVD F14, 320(X2)
- MOVD F15, 328(X2)
- MOVD F16, 336(X2)
- MOVD F17, 344(X2)
- MOVD F18, 352(X2)
- MOVD F19, 360(X2)
- MOVD F20, 368(X2)
- MOVD F21, 376(X2)
- MOVD F22, 384(X2)
- MOVD F23, 392(X2)
- MOVD F24, 400(X2)
- MOVD F25, 408(X2)
- MOVD F26, 416(X2)
- MOVD F27, 424(X2)
- MOVD F28, 432(X2)
- MOVD F29, 440(X2)
- MOVD F30, 448(X2)
- MOVD F31, 456(X2)
+ MOV X9, 32(X2)
+ MOV X10, 40(X2)
+ MOV X11, 48(X2)
+ MOV X12, 56(X2)
+ MOV X13, 64(X2)
+ MOV X14, 72(X2)
+ MOV X15, 80(X2)
+ MOV X16, 88(X2)
+ MOV X17, 96(X2)
+ MOV X18, 104(X2)
+ MOV X19, 112(X2)
+ MOV X20, 120(X2)
+ MOV X21, 128(X2)
+ MOV X22, 136(X2)
+ MOV X23, 144(X2)
+ MOV X24, 152(X2)
+ MOV X25, 160(X2)
+ MOV X26, 168(X2)
+ MOV X28, 176(X2)
+ MOV X29, 184(X2)
+ MOV X30, 192(X2)
+ MOVD F0, 200(X2)
+ MOVD F1, 208(X2)
+ MOVD F2, 216(X2)
+ MOVD F3, 224(X2)
+ MOVD F4, 232(X2)
+ MOVD F5, 240(X2)
+ MOVD F6, 248(X2)
+ MOVD F7, 256(X2)
+ MOVD F8, 264(X2)
+ MOVD F9, 272(X2)
+ MOVD F10, 280(X2)
+ MOVD F11, 288(X2)
+ MOVD F12, 296(X2)
+ MOVD F13, 304(X2)
+ MOVD F14, 312(X2)
+ MOVD F15, 320(X2)
+ MOVD F16, 328(X2)
+ MOVD F17, 336(X2)
+ MOVD F18, 344(X2)
+ MOVD F19, 352(X2)
+ MOVD F20, 360(X2)
+ MOVD F21, 368(X2)
+ MOVD F22, 376(X2)
+ MOVD F23, 384(X2)
+ MOVD F24, 392(X2)
+ MOVD F25, 400(X2)
+ MOVD F26, 408(X2)
+ MOVD F27, 416(X2)
+ MOVD F28, 424(X2)
+ MOVD F29, 432(X2)
+ MOVD F30, 440(X2)
+ MOVD F31, 448(X2)
CALL ·asyncPreempt2(SB)
- MOVD 456(X2), F31
- MOVD 448(X2), F30
- MOVD 440(X2), F29
- MOVD 432(X2), F28
- MOVD 424(X2), F27
- MOVD 416(X2), F26
- MOVD 408(X2), F25
- MOVD 400(X2), F24
- MOVD 392(X2), F23
- MOVD 384(X2), F22
- MOVD 376(X2), F21
- MOVD 368(X2), F20
- MOVD 360(X2), F19
- MOVD 352(X2), F18
- MOVD 344(X2), F17
- MOVD 336(X2), F16
- MOVD 328(X2), F15
- MOVD 320(X2), F14
- MOVD 312(X2), F13
- MOVD 304(X2), F12
- MOVD 296(X2), F11
- MOVD 288(X2), F10
- MOVD 280(X2), F9
- MOVD 272(X2), F8
- MOVD 264(X2), F7
- MOVD 256(X2), F6
- MOVD 248(X2), F5
- MOVD 240(X2), F4
- MOVD 232(X2), F3
- MOVD 224(X2), F2
- MOVD 216(X2), F1
- MOVD 208(X2), F0
- MOV 200(X2), X30
- MOV 192(X2), X29
- MOV 184(X2), X28
- MOV 176(X2), X26
- MOV 168(X2), X25
- MOV 160(X2), X24
- MOV 152(X2), X23
- MOV 144(X2), X22
- MOV 136(X2), X21
- MOV 128(X2), X20
- MOV 120(X2), X19
- MOV 112(X2), X18
- MOV 104(X2), X17
- MOV 96(X2), X16
- MOV 88(X2), X15
- MOV 80(X2), X14
- MOV 72(X2), X13
- MOV 64(X2), X12
- MOV 56(X2), X11
- MOV 48(X2), X10
- MOV 40(X2), X9
- MOV 32(X2), X8
+ MOVD 448(X2), F31
+ MOVD 440(X2), F30
+ MOVD 432(X2), F29
+ MOVD 424(X2), F28
+ MOVD 416(X2), F27
+ MOVD 408(X2), F26
+ MOVD 400(X2), F25
+ MOVD 392(X2), F24
+ MOVD 384(X2), F23
+ MOVD 376(X2), F22
+ MOVD 368(X2), F21
+ MOVD 360(X2), F20
+ MOVD 352(X2), F19
+ MOVD 344(X2), F18
+ MOVD 336(X2), F17
+ MOVD 328(X2), F16
+ MOVD 320(X2), F15
+ MOVD 312(X2), F14
+ MOVD 304(X2), F13
+ MOVD 296(X2), F12
+ MOVD 288(X2), F11
+ MOVD 280(X2), F10
+ MOVD 272(X2), F9
+ MOVD 264(X2), F8
+ MOVD 256(X2), F7
+ MOVD 248(X2), F6
+ MOVD 240(X2), F5
+ MOVD 232(X2), F4
+ MOVD 224(X2), F3
+ MOVD 216(X2), F2
+ MOVD 208(X2), F1
+ MOVD 200(X2), F0
+ MOV 192(X2), X30
+ MOV 184(X2), X29
+ MOV 176(X2), X28
+ MOV 168(X2), X26
+ MOV 160(X2), X25
+ MOV 152(X2), X24
+ MOV 144(X2), X23
+ MOV 136(X2), X22
+ MOV 128(X2), X21
+ MOV 120(X2), X20
+ MOV 112(X2), X19
+ MOV 104(X2), X18
+ MOV 96(X2), X17
+ MOV 88(X2), X16
+ MOV 80(X2), X15
+ MOV 72(X2), X14
+ MOV 64(X2), X13
+ MOV 56(X2), X12
+ MOV 48(X2), X11
+ MOV 40(X2), X10
+ MOV 32(X2), X9
MOV 24(X2), X7
MOV 16(X2), X6
MOV 8(X2), X5
MOV 464(X2), X1
+ MOV -8(X2), X8
MOV (X2), X31
- ADD $472, X2
+ ADD $480, X2
JMP (X31)
+
diff --git a/src/runtime/proc.go b/src/runtime/proc.go
index db4feba..5b9274b 100644
--- a/src/runtime/proc.go
+++ b/src/runtime/proc.go
@@ -5372,7 +5372,7 @@
*(*uintptr)(unsafe.Pointer(sp)) = 0
prepGoExitFrame(sp)
}
- if GOARCH == "arm64" {
+ if GOARCH == "arm64" || GOARCH == "riscv64" {
// caller's FP
*(*uintptr)(unsafe.Pointer(sp - goarch.PtrSize)) = 0
}
diff --git a/src/runtime/runtime2.go b/src/runtime/runtime2.go
index 9fec6c6..2968ead 100644
--- a/src/runtime/runtime2.go
+++ b/src/runtime/runtime2.go
@@ -1505,7 +1505,7 @@
)
// Must agree with internal/buildcfg.FramePointerEnabled.
-const framepointer_enabled = GOARCH == "amd64" || GOARCH == "arm64"
+const framepointer_enabled = GOARCH == "amd64" || GOARCH == "arm64" || GOARCH == "riscv64"
// getcallerfp returns the frame pointer of the caller of the caller
// of this function.
@@ -1515,8 +1515,16 @@
func getcallerfp() uintptr {
fp := getfp() // This frame's FP.
if fp != 0 {
- fp = *(*uintptr)(unsafe.Pointer(fp)) // The caller's FP.
- fp = *(*uintptr)(unsafe.Pointer(fp)) // The caller's caller's FP.
+ if GOARCH == "riscv64" {
+ // On RISC-V, FP (S0) points to SP+8.
+ // The caller's FP is saved at SP-8, which is fp-16.
+ fp = *(*uintptr)(unsafe.Pointer(fp - 16)) // The caller's FP.
+ fp = *(*uintptr)(unsafe.Pointer(fp - 16)) // The caller's caller's FP.
+ } else {
+ // On ARM64/AMD64, FP points exactly to the saved FP.
+ fp = *(*uintptr)(unsafe.Pointer(fp)) // The caller's FP.
+ fp = *(*uintptr)(unsafe.Pointer(fp)) // The caller's caller's FP.
+ }
}
return fp
}
diff --git a/src/runtime/signal_riscv64.go b/src/runtime/signal_riscv64.go
index 8acd34c..5194f40 100644
--- a/src/runtime/signal_riscv64.go
+++ b/src/runtime/signal_riscv64.go
@@ -63,10 +63,15 @@
// functions are correctly handled. This smashes
// the stack frame but we're not going back there
// anyway.
- sp := c.sp() - goarch.PtrSize
+ sp := c.sp() - 2*goarch.PtrSize
c.set_sp(sp)
*(*uint64)(unsafe.Pointer(uintptr(sp))) = c.ra()
-
+ // Make sure a valid frame pointer is saved on the stack so that the
+ // frame pointer checks in adjustframe are happy, if they're enabled.
+ // Frame pointer unwinding won't visit the sigpanic frame, since
+ // sigpanic will save the same frame pointer before calling into a panic
+ // function.
+ *(*uint64)(unsafe.Pointer(uintptr(sp - goarch.PtrSize))) = c.s0()
pc := gp.sigpc
if shouldPushSigpanic(gp, pc, uintptr(c.ra())) {
@@ -84,9 +89,13 @@
// push the call. The function being pushed is responsible
// for restoring the LR and setting the SP back.
// This extra slot is known to gentraceback.
- sp := c.sp() - goarch.PtrSize
+ sp := c.sp() - 2*goarch.PtrSize
c.set_sp(sp)
*(*uint64)(unsafe.Pointer(uintptr(sp))) = c.ra()
+ // Make sure a valid frame pointer is saved on the stack so that the
+ // frame pointer checks in adjustframe are happy, if they're enabled.
+ // This is not actually used for unwinding.
+ *(*uint64)(unsafe.Pointer(uintptr(sp - goarch.PtrSize))) = c.s0()
// Set up PC and LR to pretend the function being signaled
// calls targetPC at resumePC.
c.set_ra(uint64(resumePC))
diff --git a/src/runtime/stack.go b/src/runtime/stack.go
index 6f89cc1..9c18a55 100644
--- a/src/runtime/stack.go
+++ b/src/runtime/stack.go
@@ -709,7 +709,7 @@
}
// Adjust saved frame pointer if there is one.
- if (goarch.ArchFamily == goarch.AMD64 || goarch.ArchFamily == goarch.ARM64) && frame.argp-frame.varp == 2*goarch.PtrSize {
+ if (goarch.ArchFamily == goarch.AMD64 || goarch.ArchFamily == goarch.ARM64 || goarch.ArchFamily == goarch.RISCV64) && frame.argp-frame.varp == 2*goarch.PtrSize {
if stackDebug >= 3 {
print(" saved bp\n")
}
@@ -725,8 +725,8 @@
}
// On AMD64, this is the caller's frame pointer saved in the current
// frame.
- // On ARM64, this is the frame pointer of the caller's caller saved
- // by the caller in its frame (one word below its SP).
+ // On ARM64 and RISCV64, this is the frame pointer of the caller's
+ // caller saved by the caller in its frame (one word below its SP).
adjustpointer(adjinfo, unsafe.Pointer(frame.varp))
}
@@ -796,6 +796,15 @@
memmove(unsafe.Pointer(gp.sched.bp), unsafe.Pointer(oldfp), goarch.PtrSize)
adjustpointer(adjinfo, unsafe.Pointer(gp.sched.bp))
}
+ } else if GOARCH == "riscv64" {
+ // On RISCV64, the frame pointer (S0/X8) points one word above SP,
+ // while the frame pointer is saved one word *below* SP.
+ if oldfp == gp.sched.sp+goarch.PtrSize {
+ oldlink := oldfp - 2*goarch.PtrSize
+ newlink := gp.sched.bp - 2*goarch.PtrSize
+ memmove(unsafe.Pointer(newlink), unsafe.Pointer(oldlink), goarch.PtrSize)
+ adjustpointer(adjinfo, unsafe.Pointer(newlink))
+ }
}
}
diff --git a/src/runtime/stubs_riscv64.go b/src/runtime/stubs_riscv64.go
index 2306ba8..e1f91cd 100644
--- a/src/runtime/stubs_riscv64.go
+++ b/src/runtime/stubs_riscv64.go
@@ -22,6 +22,4 @@
// getfp returns the frame pointer register of its caller or 0 if not implemented.
// TODO: Make this a compiler intrinsic
-//
-//go:nosplit
-func getfp() uintptr { return 0 }
+func getfp() uintptr
diff --git a/src/runtime/traceback.go b/src/runtime/traceback.go
index efea4d8..e431352 100644
--- a/src/runtime/traceback.go
+++ b/src/runtime/traceback.go
@@ -501,7 +501,11 @@
// before faking a call.
if usesLR && injectedCall {
x := *(*uintptr)(unsafe.Pointer(frame.sp))
- frame.sp += alignUp(sys.MinFrameSize, sys.StackAlign)
+ if goarch.ArchFamily == goarch.RISCV64 && framepointer_enabled {
+ frame.sp += 2 * goarch.PtrSize
+ } else {
+ frame.sp += alignUp(sys.MinFrameSize, sys.StackAlign)
+ }
f = findfunc(frame.pc)
frame.fn = f
if !f.valid() {
diff --git a/src/runtime/tracestack.go b/src/runtime/tracestack.go
index d3f217b..3380647 100644
--- a/src/runtime/tracestack.go
+++ b/src/runtime/tracestack.go
@@ -257,7 +257,7 @@
// tracefpunwindoff returns true if frame pointer unwinding for the tracer is
// disabled via GODEBUG or not supported by the architecture.
func tracefpunwindoff() bool {
- return debug.tracefpunwindoff != 0 || (goarch.ArchFamily != goarch.AMD64 && goarch.ArchFamily != goarch.ARM64)
+ return debug.tracefpunwindoff != 0 || (goarch.ArchFamily != goarch.AMD64 && goarch.ArchFamily != goarch.ARM64 && goarch.ArchFamily != goarch.RISCV64)
}
// fpTracebackPCs populates pcBuf with the return addresses for each frame and
@@ -266,10 +266,18 @@
// B, this will return a PC for only B.
func fpTracebackPCs(fp unsafe.Pointer, pcBuf []uintptr) (i int) {
for i = 0; i < len(pcBuf) && fp != nil; i++ {
- // return addr sits one word above the frame pointer
- pcBuf[i] = *(*uintptr)(unsafe.Pointer(uintptr(fp) + goarch.PtrSize))
- // follow the frame pointer to the next one
- fp = unsafe.Pointer(*(*uintptr)(fp))
+ if GOARCH == "riscv64" {
+ // On RISC-V, the frame pointer (FP) points to SP+PtrSize.
+ // The return address (LR) is at SP+0, which is fp-PtrSize.
+ pcBuf[i] = *(*uintptr)(unsafe.Pointer(uintptr(fp) - goarch.PtrSize))
+ // The saved caller FP is at SP-PtrSize, which is fp-2*PtrSize.
+ fp = unsafe.Pointer(*(*uintptr)(unsafe.Pointer(uintptr(fp) - 2*goarch.PtrSize)))
+ } else {
+ // return addr sits one word above the frame pointer
+ pcBuf[i] = *(*uintptr)(unsafe.Pointer(uintptr(fp) + goarch.PtrSize))
+ // follow the frame pointer to the next one
+ fp = unsafe.Pointer(*(*uintptr)(fp))
+ }
}
return i
}
diff --git a/test/nosplit.go b/test/nosplit.go
index 4b4c93b..c2a965b 100644
--- a/test/nosplit.go
+++ b/test/nosplit.go
@@ -146,7 +146,7 @@
start 108 nosplit; REJECT ppc64 ppc64le
start 112 nosplit; REJECT ppc64 ppc64le arm64
start 116 nosplit; REJECT ppc64 ppc64le
-start 120 nosplit; REJECT ppc64 ppc64le amd64 arm64
+start 120 nosplit; REJECT ppc64 ppc64le amd64 arm64 riscv64
start 124 nosplit; REJECT ppc64 ppc64le amd64
start 128 nosplit; REJECT
start 132 nosplit; REJECT
@@ -164,7 +164,7 @@
start 108 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le
start 112 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le amd64 arm64
start 116 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le amd64
-start 120 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le amd64 arm64
+start 120 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le amd64 arm64 riscv64
start 124 nosplit call f; f 0 nosplit; REJECT ppc64 ppc64le amd64 386
start 128 nosplit call f; f 0 nosplit; REJECT
start 132 nosplit call f; f 0 nosplit; REJECT
@@ -180,7 +180,7 @@
start 108 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64
start 112 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64 arm64
start 116 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64
-start 120 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64 386 arm64
+start 120 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64 386 arm64 riscv64
start 124 nosplit call f; f 0 call f; REJECT ppc64 ppc64le amd64 386
start 128 nosplit call f; f 0 call f; REJECT
start 132 nosplit call f; f 0 call f; REJECT
@@ -193,7 +193,7 @@
start 108 nosplit callind; REJECT ppc64 ppc64le amd64
start 112 nosplit callind; REJECT ppc64 ppc64le amd64 arm64
start 116 nosplit callind; REJECT ppc64 ppc64le amd64
-start 120 nosplit callind; REJECT ppc64 ppc64le amd64 386 arm64
+start 120 nosplit callind; REJECT ppc64 ppc64le amd64 386 arm64 riscv64
start 124 nosplit callind; REJECT ppc64 ppc64le amd64 386
start 128 nosplit callind; REJECT
start 132 nosplit callind; REJECT
Change information
Files:
- M src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
- M src/cmd/compile/internal/ssa/opGen.go
- M src/cmd/internal/obj/riscv/obj.go
- M src/crypto/internal/fips140/bigmod/nat_riscv64.s
- M src/crypto/internal/fips140/sha256/sha256block_riscv64.s
- M src/crypto/internal/fips140/sha512/sha512block_riscv64.s
- M src/crypto/internal/fips140/subtle/xor_riscv64.s
- M src/crypto/md5/md5block_riscv64.s
- M src/crypto/sha1/sha1block_riscv64.s
- M src/internal/abi/abi_riscv64.go
- M src/internal/buildcfg/exp.go
- M src/internal/bytealg/compare_riscv64.s
- M src/math/big/arith_riscv64.s
- M src/math/big/internal/asmgen/riscv64.go
- M src/runtime/asan_riscv64.s
- M src/runtime/asm_riscv64.s
- M src/runtime/cgo/asm_riscv64.s
- M src/runtime/mkpreempt.go
- M src/runtime/mprof.go
- M src/runtime/panic.go
- M src/runtime/preempt_riscv64.s
- M src/runtime/proc.go
- M src/runtime/runtime2.go
- M src/runtime/signal_riscv64.go
- M src/runtime/stack.go
- M src/runtime/stubs_riscv64.go
- M src/runtime/traceback.go
- M src/runtime/tracestack.go
- M test/nosplit.go
Change size: XL
Delta: 29 files changed, 1026 insertions(+), 877 deletions(-)
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Keith Randall (Gerrit)
Mar 12, 2026, 10:49:45 PM (6 days ago) Mar 12
to Boyao Wang, goph...@pubsubhelper.golang.org, Keith Randall, Joel Sing, Meng Zhuo, Mark Ryan, Pengcheng Wang, Gopher Robot, golang-co...@googlegroups.com
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Keith Randall added 1 comment![]( "Open in Gerrit")
Patchset-level comments
File-level comment, Patchset 1 (Latest):
Keith Randall . unresolved
I'm actually trying to fix the framepointer implementation for arm64 (see CL 674615). So that might not be the right implementation to model.
The particular problem there is storing FP at SP-8. That really complicates things like interrupts that expect to be able to modify data below SP. I plan on moving to something closer to x86, where the fp and return value are at the top of the frame, not the bottom.
Maybe not a showstopper here? But something to think about.
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Boyao Wang (Gerrit)
8:01 AM (8 hours ago) 8:01 AM
to goph...@pubsubhelper.golang.org, golang-co...@googlegroups.com
Attention needed from Boyao Wang, Mark Ryan and Meng Zhuo
Boyao Wang uploaded new patchset![]( "Open in Gerrit")
Boyao Wang uploaded patch set #2 to this change.
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