[go/dev.simd] [dev.simd] simd, cmd/compile: add WASM SIMD first steps
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David Chase (Gerrit)
Feb 12, 2026, 3:10:34 PMFeb 12
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[dev.simd] simd, cmd/compile: add WASM SIMD first steps
DO NOT SUBMIT
WIP
Change-Id: Ifbbe7f5a705799a77b4f0092042f02e1b31e9fd6
Change diff
Change information
Files:
- M src/cmd/compile/internal/ssa/_gen/WasmOps.go
- M src/cmd/compile/internal/ssa/_gen/genericOps.go
- A src/cmd/compile/internal/ssa/_gen/simdWasm.rules
- A src/cmd/compile/internal/ssa/_gen/simdWasmops.go
- A src/cmd/compile/internal/ssa/_gen/simdgenericOps_Wasm.go
- M src/cmd/compile/internal/ssa/opGen.go
- M src/cmd/compile/internal/ssa/rewriteWasm.go
- A src/cmd/compile/internal/ssagen/simdWasmintrinsics.go
- A src/cmd/compile/internal/wasm/simdssa.go
- M src/cmd/compile/internal/wasm/ssa.go
- M src/simd/archsimd/_gen/simdgen/gen_simdTypes.go
- A src/simd/archsimd/_gen/wasmgen/main.go
- M src/simd/archsimd/cpu.go
- M src/simd/archsimd/ops_amd64.go
- M src/simd/archsimd/ops_internal_amd64.go
- A src/simd/archsimd/ops_wasm.go
- M src/simd/archsimd/types_amd64.go
- A src/simd/archsimd/types_wasm.go
Change size: XL
Delta: 18 files changed, 7536 insertions(+), 314 deletions(-)
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David Chase (Gerrit)
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David Chase (Gerrit)
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David Chase (Gerrit)
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David Chase (Gerrit)
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David Chase (Gerrit)
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David Chase (Gerrit)
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David Chase (Gerrit)
Mar 24, 2026, 11:52:23 PMMar 24
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David Chase (Gerrit)
Mar 25, 2026, 1:13:00 AMMar 25
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Junyang Shao (Gerrit)
Apr 13, 2026, 3:40:23 PMApr 13
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David Chase (Gerrit)
Apr 17, 2026, 2:03:26 PMApr 17
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Cherry Mui (Gerrit)
Apr 17, 2026, 6:42:05 PMApr 17
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Cherry Mui added 9 comments![]( "Open in Gerrit")
Patchset-level comments
File-level comment, Patchset 13 (Latest):
Cherry Mui . resolved
First round of review. Looks good overall. Thanks.
File src/cmd/compile/internal/ssa/_gen/genericOps.go
Line 757, Patchset 13 (Latest):
genericOps = append(genericOps, simdGenericOps()...)
genericOps = append(genericOps, simdGenericOpsWasm()...)Cherry Mui . unresolved
This suggests that our existing simdGenericOps are still architecture dependent, in that they are generic ops, but corresponding to a specific architecture. Maybe we should rename? Maybe we should find another way to enumerate all generic ops?
File src/cmd/compile/internal/ssa/_gen/simdgenericOps_Wasm.go
Line 9, Patchset 13 (Latest):
{name: "AndMask8x16", argLength: 2, commutative: true},
{name: "AndMask16x8", argLength: 2, commutative: true},
{name: "AndMask32x4", argLength: 2, commutative: true},
{name: "AndMask64x2", argLength: 2, commutative: true},
{name: "AndNotMask8x16", argLength: 2},
{name: "AndNotMask16x8", argLength: 2},
{name: "AndNotMask32x4", argLength: 2},
{name: "AndNotMask64x2", argLength: 2},Cherry Mui . unresolved
It looks like Mask types are just int vector types, the same as AMD64. On AMD64 we don't need Mask ops as generic ops. Instead, we just intrinsify Mask8x18.And to AndInt8x16. Can we do the same for Wasm?
File src/simd/archsimd/_gen/simdgen/gen_simdTypes.go
Line 158, Patchset 13 (Latest):
//go:build goexperiment.simd && amd64Cherry Mui . unresolved
We probably don't want this. See other comments. Some files are available on all architectures, like cpu.go. Other files use _amd64 suffix in the file name as the constraint.
File src/simd/archsimd/cpu.go
Line 3, Patchset 13 (Latest):
//go:build goexperiment.simd && amd64Cherry Mui . unresolved
The doc comments below says that the features are defined on all architectures, just return false if it is not X86. So I think we should not make this change.
File src/simd/archsimd/dummy.s
Line 5, Patchset 13 (Latest):
//go:build amd64||wasmCherry Mui . unresolved
Add a space before and after ||.
File src/simd/archsimd/ops_amd64.go
Line 3, Patchset 13 (Latest):
//go:build goexperiment.simd && amd64Cherry Mui . unresolved
The build constraint is implied by the file name, so this shouldn't be necessary.
File src/simd/archsimd/ops_wasm.go
Line 8, Patchset 13 (Latest):
// i8x16.absCherry Mui . unresolved
We should format this in the same way as amd64.
File src/simd/archsimd/types_wasm.go
Line 302, Patchset 13 (Latest):
// Mask8x16 is a 128-bit SIMD vector of 16 int8s.Cherry Mui . unresolved
This is for a vector type, not a mask type.
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David Chase (Gerrit)
Apr 21, 2026, 3:28:02 PMApr 21
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David Chase added 7 comments![]( "Open in Gerrit")
Patchset-level comments
File-level comment, Patchset 14 (Latest):
David Chase . resolved
All but two comments addressed so far, want to remail the stack and iterate.
File src/cmd/compile/internal/ssa/_gen/genericOps.go
Line 757, Patchset 13:
genericOps = append(genericOps, simdGenericOps()...)
genericOps = append(genericOps, simdGenericOpsWasm()...)Cherry Mui . resolved
This suggests that our existing simdGenericOps are still architecture dependent, in that they are generic ops, but corresponding to a specific architecture. Maybe we should rename? Maybe we should find another way to enumerate all generic ops?
David Chase
I think I might want to figure this out in a separate CL, because it will involve coordinating with AMD64 while other changes are in flight.
File src/simd/archsimd/_gen/simdgen/gen_simdTypes.go
We probably don't want this. See other comments. Some files are available on all architectures, like cpu.go. Other files use _amd64 suffix in the file name as the constraint.
David Chase
Done
File src/simd/archsimd/cpu.go
The doc comments below says that the features are defined on all architectures, just return false if it is not X86. So I think we should not make this change.
David Chase
Done
File src/simd/archsimd/dummy.s
Add a space before and after ||.
David Chase
Done
File src/simd/archsimd/ops_amd64.go
The build constraint is implied by the file name, so this shouldn't be necessary.
David Chase
Done
File src/simd/archsimd/types_wasm.go
This is for a vector type, not a mask type.
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File src/cmd/compile/internal/ssa/_gen/simdgenericOps_Wasm.go
Line 9, Patchset 13:
{name: "AndMask8x16", argLength: 2, commutative: true},
{name: "AndMask16x8", argLength: 2, commutative: true},
{name: "AndMask32x4", argLength: 2, commutative: true},
{name: "AndMask64x2", argLength: 2, commutative: true},
{name: "AndNotMask8x16", argLength: 2},
{name: "AndNotMask16x8", argLength: 2},
{name: "AndNotMask32x4", argLength: 2},
{name: "AndNotMask64x2", argLength: 2},Cherry Mui . resolved
It looks like Mask types are just int vector types, the same as AMD64. On AMD64 we don't need Mask ops as generic ops. Instead, we just intrinsify Mask8x18.And to AndInt8x16. Can we do the same for Wasm?
David Chase
Done
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File src/simd/archsimd/ops_wasm.go
Line 8, Patchset 13:
// i8x16.absCherry Mui . resolved
David ChaseWe should format this in the same way as amd64.
Done
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David Chase (Gerrit)
May 4, 2026, 5:06:59 PM (7 days ago) May 4
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David Chase (Gerrit)
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May 8, 2026, 2:30:05 PM (3 days ago) May 8
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File src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
Line 22, Patchset 21 (Latest):
{name: "AbsInt8x16", argLength: 1}, // ARCH:amd64Junyang Shao . unresolved
Is this right? Shouldn't it be ARCH:amd64,wasm ?...
File src/cmd/compile/internal/wasm/simdssa.go
Line 14, Patchset 21 (Latest):
case ssa.OpWasmI8x16AllTrue:
getValue128(s, v.Args[0])
s.Prog(v.Op.Asm())
case ssa.OpWasmV128AnyTrue:
getValue128(s, v.Args[0])
s.Prog(v.Op.Asm())Junyang Shao . unresolved
Can merge them?
There are many other similarly mergeable places too
File src/simd/archsimd/_gen/simdgen/gen_simdGenericOps.go
Line 1, Patchset 21 (Latest):
// Copyright 2025 The Go Authors. All rights reserved.Junyang Shao . unresolved
Should these belong to CL 772102?
File src/simd/archsimd/_gen/simdgen/godefs.go
File src/simd/archsimd/ops_wasm.go
Line 237, Patchset 21 (Latest):
// Bitselect returns the elementwise bitwise selection using mask m.Junyang Shao . unresolved
BitSelect?
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David Chase (Gerrit)
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David Chase (Gerrit)
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File src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
Is this right? Shouldn't it be ARCH:amd64,wasm ?...
David Chase
It should, if Wasm had that instruction, but it does not. Floating point only.
vunopf𝑁x𝑀 ::= abs | neg | sqrt | ceil | floor | trunc | nearest
File src/cmd/compile/internal/wasm/simdssa.go
Line 14, Patchset 21:
case ssa.OpWasmI8x16AllTrue:
getValue128(s, v.Args[0])
s.Prog(v.Op.Asm())
case ssa.OpWasmV128AnyTrue:
getValue128(s, v.Args[0])
s.Prog(v.Op.Asm())Junyang Shao . resolved
Can merge them?
There are many other similarly mergeable places too
David Chase
This file is all merged now.
File src/simd/archsimd/_gen/simdgen/gen_simdGenericOps.go
Should these belong to CL 772102?
David Chase
It could go there, so I did that. Originally the Musman fixes had not landed yet.
The AI-suggested fix is irrelevant and would probably provoke a copyright-test failure, be sure to tell the robot it made a mistake.
File src/simd/archsimd/_gen/simdgen/godefs.go
Should these belong to CL 772102?
David Chase
Done
File src/simd/archsimd/ops_wasm.go
Line 237, Patchset 21:
// Bitselect returns the elementwise bitwise selection using mask m.Junyang Shao . resolved
David ChaseBitSelect?
I fixed the declaration/documentation; we might not want this for all the types, but for now it is.
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Cherry Mui (Gerrit)
May 8, 2026, 6:06:53 PM (3 days ago) May 8
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Cherry Mui voted and added 6 comments![]( "Open in Gerrit")
Votes added by Cherry Mui
| Code-Review | +1 |
6 comments
Patchset-level comments
File-level comment, Patchset 24 (Latest):
Cherry Mui . resolved
Looks good overall. The compiler change looks good. Haven't looked carfully on the generator. Thanks.
File src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Line 1534, Patchset 24 (Latest):
simdregmask: fp,Cherry Mui . unresolved
Let's use v. (v and fp are equal, just for clarity.)
File src/cmd/compile/internal/ssa/_gen/WasmOps.go
Line 25, Patchset 24 (Latest):
// "R15", // because the register allocator currently has a 64-register limit, exclude a few registers.Cherry Mui . unresolved
The limit no longer applies. Maybe we don't need this now.
File src/cmd/compile/internal/ssa/regalloc.go
Line 689, Patchset 24 (Latest):
sourceMask := s.compatRegs(v.Type)
if !sourceMask.hasReg(r) && !onWasmStack {
// Assign a temporary register that can be copied to the desired destination;
// this at least works where it is currently a problem (x86).
// This happens processing e.g. ASAN/TSAN with SIMD *simdtype methods.
s.setOrig(c, v)
s.assignReg(s.allocReg(sourceMask, v), v, c)
c = s.curBlock.NewValue1(pos, OpCopy, v.Type, c)
}Cherry Mui . unresolved
This seems unrelated to this CL? Maybe another CL?
File src/cmd/compile/internal/ssagen/intrinsics.go
Line 1977, Patchset 24 (Latest):
if base.Ctxt.Retpoline {
// Note spectre=all implies retpoline which requires binary search instead of table switch.
return branchTableImm8(s, idx, intrinsicCall, genOp)
}
Cherry Mui . unresolved
This may be another CL.
Line 1990, Patchset 24 (Parent):
if base.Flag.Cfg.SpectreIndex {
// Potential Spectre vulnerability hardening?
idx = s.newValue2(ssa.OpSpectreSliceIndex, t, idx, s.uintptrConstant(255))
}Cherry Mui . unresolved
For spectre=index but not all, we may need this? Either way, should be another CL.
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David Chase (Gerrit)
May 8, 2026, 8:55:53 PM (3 days ago) May 8
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David Chase uploaded new patchset![]( "Open in Gerrit")
David Chase uploaded patch set #25 to this change.
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David Chase (Gerrit)
May 8, 2026, 8:58:34 PM (3 days ago) May 8
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David Chase added 5 comments![]( "Open in Gerrit")
File src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Let's use v. (v and fp are equal, just for clarity.)
David Chase
Done
File src/cmd/compile/internal/ssa/_gen/WasmOps.go
Line 25, Patchset 24:
// "R15", // because the register allocator currently has a 64-register limit, exclude a few registers.Cherry Mui . resolved
The limit no longer applies. Maybe we don't need this now.
David Chase
Done
File src/cmd/compile/internal/ssa/regalloc.go
Line 689, Patchset 24:
sourceMask := s.compatRegs(v.Type)
if !sourceMask.hasReg(r) && !onWasmStack {
// Assign a temporary register that can be copied to the desired destination;
// this at least works where it is currently a problem (x86).
// This happens processing e.g. ASAN/TSAN with SIMD *simdtype methods.
s.setOrig(c, v)
s.assignReg(s.allocReg(sourceMask, v), v, c)
c = s.curBlock.NewValue1(pos, OpCopy, v.Type, c)
}Cherry Mui . resolved
This seems unrelated to this CL? Maybe another CL?
David Chase
I moved it into its own CL. The bug, now disappeared, occurred in the "use uint8 for shift distance" CL that has been abandoned, and I can't figure out how to make it happen again.
File src/cmd/compile/internal/ssagen/intrinsics.go
Line 1977, Patchset 24:
if base.Ctxt.Retpoline {
// Note spectre=all implies retpoline which requires binary search instead of table switch.
return branchTableImm8(s, idx, intrinsicCall, genOp)
}
Cherry Mui . resolved
This may be another CL.
David Chase
This is bringing this code in line with the main repository. I stole this code to fix the SIMD-retpoline bug there, and then fixed it and tweaked it along the way. Not matching exactly means extra fun for the next merge.
Line 1990, Patchset 24 (Parent):
if base.Flag.Cfg.SpectreIndex {
// Potential Spectre vulnerability hardening?
idx = s.newValue2(ssa.OpSpectreSliceIndex, t, idx, s.uintptrConstant(255))
}Cherry Mui . resolved
For spectre=index but not all, we may need this? Either way, should be another CL.
David Chase
We did not seem to need this; I could not make it fail without it, and Keith thinks that because it does all of the values, it does not apply. It matches the main repo.
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David Chase (Gerrit)
May 8, 2026, 9:22:14 PM (3 days ago) May 8
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David Chase voted![]( "Open in Gerrit")
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David Chase (Gerrit)
May 8, 2026, 9:22:49 PM (3 days ago) May 8
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David Chase voted TryBot-Bypass+0![]( "Open in Gerrit")
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David Chase (Gerrit)
May 8, 2026, 9:51:59 PM (3 days ago) May 8
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David Chase voted and added 1 comment![]( "Open in Gerrit")
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Alexander Musman (Gerrit)
May 9, 2026, 7:07:15 AM (3 days ago) May 9
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Alexander Musman added 1 comment![]( "Open in Gerrit")
File src/simd/archsimd/slicepart_128.go
Line 56, Patchset 26 (Latest):
// If s has 16 or more elements, the function is equivalent to LoadInt8x16Slice.Alexander Musman . unresolved
I noticed the new slicepart_128.go still has a few stale *Slice references in comments from before the load/store rename. Fixing them would help git auto-merge cleanly regardless of whether this CL or CL 752803 (ARM64 SIMD) lands first:
```
sed -i 's/LoadInt8x16Slice/LoadInt8x16/g; s/LoadInt16x8Slice/LoadInt16x8/g; s/LoadUint8x16Slice/LoadUint8x16/g; s/LoadUint16x8Slice/LoadUint16x8/g; s/x\.StoreSlice/x.Store/g' src/simd/archsimd/slicepart_128.go
```
Lines 56, 109, 161, 194, 228, 253.
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David Chase (Gerrit)
4:56 PM (6 hours ago) 4:56 PM
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David Chase uploaded new patchset![]( "Open in Gerrit")
David Chase uploaded patch set #28 to this change.
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David Chase (Gerrit)
5:02 PM (6 hours ago) 5:02 PM
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David Chase added 1 comment![]( "Open in Gerrit")
File src/simd/archsimd/slicepart_128.go
Line 56, Patchset 26:
// If s has 16 or more elements, the function is equivalent to LoadInt8x16Slice.Alexander Musman . resolved
I noticed the new slicepart_128.go still has a few stale *Slice references in comments from before the load/store rename. Fixing them would help git auto-merge cleanly regardless of whether this CL or CL 752803 (ARM64 SIMD) lands first:
```
sed -i 's/LoadInt8x16Slice/LoadInt8x16/g; s/LoadInt16x8Slice/LoadInt16x8/g; s/LoadUint8x16Slice/LoadUint8x16/g; s/LoadUint16x8Slice/LoadUint16x8/g; s/x\.StoreSlice/x.Store/g' src/simd/archsimd/slicepart_128.go
```Lines 56, 109, 161, 194, 228, 253.
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