[go] cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/arch
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Vasiliy Leonenko (Gerrit)
Sep 6, 2025, 5:28:01 PMSep 6
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cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/arch
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501
Change diff
diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go
index 87ccb8c..d562e59 100644
--- a/src/cmd/asm/internal/arch/arm64.go
+++ b/src/cmd/asm/internal/arch/arm64.go
@@ -195,149 +195,6 @@
return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
}
-// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
-func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
- Rnum := (reg & 31) + int16(num<<5)
- if isAmount {
- if num < 0 || num > 7 {
- return errors.New("index shift amount is out of range")
- }
- }
- if reg <= arm64.REG_R31 && reg >= arm64.REG_R0 {
- if !isAmount {
- return errors.New("invalid register extension")
- }
- switch ext {
- case "UXTB":
- if a.Type == obj.TYPE_MEM {
- return errors.New("invalid shift for the register offset addressing mode")
- }
- a.Reg = arm64.REG_UXTB + Rnum
- case "UXTH":
- if a.Type == obj.TYPE_MEM {
- return errors.New("invalid shift for the register offset addressing mode")
- }
- a.Reg = arm64.REG_UXTH + Rnum
- case "UXTW":
- // effective address of memory is a base register value and an offset register value.
- if a.Type == obj.TYPE_MEM {
- a.Index = arm64.REG_UXTW + Rnum
- } else {
- a.Reg = arm64.REG_UXTW + Rnum
- }
- case "UXTX":
- if a.Type == obj.TYPE_MEM {
- return errors.New("invalid shift for the register offset addressing mode")
- }
- a.Reg = arm64.REG_UXTX + Rnum
- case "SXTB":
- if a.Type == obj.TYPE_MEM {
- return errors.New("invalid shift for the register offset addressing mode")
- }
- a.Reg = arm64.REG_SXTB + Rnum
- case "SXTH":
- if a.Type == obj.TYPE_MEM {
- return errors.New("invalid shift for the register offset addressing mode")
- }
- a.Reg = arm64.REG_SXTH + Rnum
- case "SXTW":
- if a.Type == obj.TYPE_MEM {
- a.Index = arm64.REG_SXTW + Rnum
- } else {
- a.Reg = arm64.REG_SXTW + Rnum
- }
- case "SXTX":
- if a.Type == obj.TYPE_MEM {
- a.Index = arm64.REG_SXTX + Rnum
- } else {
- a.Reg = arm64.REG_SXTX + Rnum
- }
- case "LSL":
- a.Index = arm64.REG_LSL + Rnum
- default:
- return errors.New("unsupported general register extension type: " + ext)
-
- }
- } else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
- switch ext {
- case "B8":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
- case "B16":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
- case "H4":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
- case "H8":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
- case "S2":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
- case "S4":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
- case "D1":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
- case "D2":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
- case "Q1":
- if isIndex {
- return errors.New("invalid register extension")
- }
- a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
- case "B":
- if !isIndex {
- return nil
- }
- a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
- a.Index = num
- case "H":
- if !isIndex {
- return nil
- }
- a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
- a.Index = num
- case "S":
- if !isIndex {
- return nil
- }
- a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
- a.Index = num
- case "D":
- if !isIndex {
- return nil
- }
- a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
- a.Index = num
- default:
- return errors.New("unsupported simd register extension type: " + ext)
- }
- } else {
- return errors.New("invalid register and extension combination")
- }
- return nil
-}
-
// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
var curQ, curSize uint16
diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 8f8f6dc..545f6c7 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -775,7 +775,7 @@
switch p.arch.Family {
case sys.ARM64:
- err := arch.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
+ err := arm64.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
if err != nil {
p.errorf("%v", err)
}
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 743d09a..4398560 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -34,6 +34,7 @@
"cmd/internal/obj"
"cmd/internal/objabi"
"encoding/binary"
+ "errors"
"fmt"
"log"
"math"
@@ -7830,3 +7831,146 @@
func pack(q uint32, arngA, arngB uint8) uint32 {
return uint32(q)<<16 | uint32(arngA)<<8 | uint32(arngB)
}
+
+// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
+func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
+ Rnum := (reg & 31) + int16(num<<5)
+ if isAmount {
+ if num < 0 || num > 7 {
+ return errors.New("index shift amount is out of range")
+ }
+ }
+ if reg <= REG_R31 && reg >= REG_R0 {
+ if !isAmount {
+ return errors.New("invalid register extension")
+ }
+ switch ext {
+ case "UXTB":
+ if a.Type == obj.TYPE_MEM {
+ return errors.New("invalid shift for the register offset addressing mode")
+ }
+ a.Reg = REG_UXTB + Rnum
+ case "UXTH":
+ if a.Type == obj.TYPE_MEM {
+ return errors.New("invalid shift for the register offset addressing mode")
+ }
+ a.Reg = REG_UXTH + Rnum
+ case "UXTW":
+ // effective address of memory is a base register value and an offset register value.
+ if a.Type == obj.TYPE_MEM {
+ a.Index = REG_UXTW + Rnum
+ } else {
+ a.Reg = REG_UXTW + Rnum
+ }
+ case "UXTX":
+ if a.Type == obj.TYPE_MEM {
+ return errors.New("invalid shift for the register offset addressing mode")
+ }
+ a.Reg = REG_UXTX + Rnum
+ case "SXTB":
+ if a.Type == obj.TYPE_MEM {
+ return errors.New("invalid shift for the register offset addressing mode")
+ }
+ a.Reg = REG_SXTB + Rnum
+ case "SXTH":
+ if a.Type == obj.TYPE_MEM {
+ return errors.New("invalid shift for the register offset addressing mode")
+ }
+ a.Reg = REG_SXTH + Rnum
+ case "SXTW":
+ if a.Type == obj.TYPE_MEM {
+ a.Index = REG_SXTW + Rnum
+ } else {
+ a.Reg = REG_SXTW + Rnum
+ }
+ case "SXTX":
+ if a.Type == obj.TYPE_MEM {
+ a.Index = REG_SXTX + Rnum
+ } else {
+ a.Reg = REG_SXTX + Rnum
+ }
+ case "LSL":
+ a.Index = REG_LSL + Rnum
+ default:
+ return errors.New("unsupported general register extension type: " + ext)
+
+ }
+ } else if reg <= REG_V31 && reg >= REG_V0 {
+ switch ext {
+ case "B8":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8B & 15) << 5)
+ case "B16":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_16B & 15) << 5)
+ case "H4":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4H & 15) << 5)
+ case "H8":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8H & 15) << 5)
+ case "S2":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2S & 15) << 5)
+ case "S4":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4S & 15) << 5)
+ case "D1":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1D & 15) << 5)
+ case "D2":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2D & 15) << 5)
+ case "Q1":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1Q & 15) << 5)
+ case "B":
+ if !isIndex {
+ return nil
+ }
+ a.Reg = REG_ELEM + (reg & 31) + ((ARNG_B & 15) << 5)
+ a.Index = num
+ case "H":
+ if !isIndex {
+ return nil
+ }
+ a.Reg = REG_ELEM + (reg & 31) + ((ARNG_H & 15) << 5)
+ a.Index = num
+ case "S":
+ if !isIndex {
+ return nil
+ }
+ a.Reg = REG_ELEM + (reg & 31) + ((ARNG_S & 15) << 5)
+ a.Index = num
+ case "D":
+ if !isIndex {
+ return nil
+ }
+ a.Reg = REG_ELEM + (reg & 31) + ((ARNG_D & 15) << 5)
+ a.Index = num
+ default:
+ return errors.New("unsupported simd register extension type: " + ext)
+ }
+ } else {
+ return errors.New("invalid register and extension combination")
+ }
+ return nil
+}
Change information
Files:
- M src/cmd/asm/internal/arch/arm64.go
- M src/cmd/asm/internal/asm/parse.go
- M src/cmd/internal/obj/arm64/asm7.go
Change size: L
Delta: 3 files changed, 145 insertions(+), 144 deletions(-)
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Keith Randall (Gerrit)
Sep 8, 2025, 2:07:51 PMSep 8
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Keith Randall voted![]( "Open in Gerrit")
| Code-Review | +2 |
| Commit-Queue | +1 |
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Cherry Mui (Gerrit)
Oct 10, 2025, 3:43:56 PM (5 days ago) Oct 10
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Keith Randall (Gerrit)
12:38 PM (11 hours ago) 12:38 PM
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Vasiliy Leonenko (Gerrit)
5:27 PM (6 hours ago) 5:27 PM
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Vasiliy Leonenko added 1 comment![]( "Open in Gerrit")
Patchset-level comments
File-level comment, Patchset 6 (Latest):
Vasiliy Leonenko . resolved
Trybot job failed for x_tools-gotip-linux-amd64, while this CL touches only sources related to arm64 platform.
After rebasing this CL on top of previous related CL I checked on amd64 (WSL Ubuntu), all.bash passed all tests.
Note: this CL was initially prepared for CL692316 (next in relation chain) to enable usage of ARM64RegisterExtension in ssaGenValue function.
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Cherry Mui (Gerrit)
8:18 PM (4 hours ago) 8:18 PM
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Cherry Mui (Gerrit)
8:35 PM (3 hours ago) 8:35 PM
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Cherry Mui submitted the change![]( "Open in Gerrit")
Change information
Commit message:
cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/arch
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501
Reviewed-on: https://go-review.googlesource.com/c/go/+/701455
Reviewed-by: Cherry Mui <cher...@google.com>
LUCI-TryBot-Result: Go LUCI <golang...@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Keith Randall <k...@google.com>
Files:
- M src/cmd/asm/internal/arch/arm64.go
- M src/cmd/asm/internal/asm/parse.go
- M src/cmd/internal/obj/arm64/asm7.go
Change size: L
Delta: 3 files changed, 145 insertions(+), 144 deletions(-)
Branch: refs/heads/master
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Code-Review: +2 by Cherry Mui, +2 by Keith Randall
TryBots-Pass: LUCI-TryBot-Result+1 by Go LUCI
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