Junyang Shao (Gerrit)

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May 26, 2026, 3:38:45 PMMay 26

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Junyang Shao has uploaded the change for review

Commit message

[dev.simd] simd, cmd/compile: SaturateToConcat -> ConcatSaturateTo

Please see discussion https://github.com/golang/go/issues/78979#issuecomment-4547906551

Change-Id: Idbe2e0efd7133e420253d69138445af39c0dc1b7

Change diff

diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go
index 3e1f5dc..3785602 100644
--- a/src/cmd/compile/internal/amd64/simdssa.go
+++ b/src/cmd/compile/internal/amd64/simdssa.go
@@ -289,6 +289,12 @@
 		ssa.OpAMD64VPHADDD256,
 		ssa.OpAMD64VPHADDSW128,
 		ssa.OpAMD64VPHADDSW256,
+		ssa.OpAMD64VPACKSSDW128,
+		ssa.OpAMD64VPACKSSDW256,
+		ssa.OpAMD64VPACKSSDW512,
+		ssa.OpAMD64VPACKUSDW128,
+		ssa.OpAMD64VPACKUSDW256,
+		ssa.OpAMD64VPACKUSDW512,
 		ssa.OpAMD64VHSUBPS128,
 		ssa.OpAMD64VHSUBPD128,
 		ssa.OpAMD64VPHSUBW128,
@@ -472,12 +478,6 @@
 		ssa.OpAMD64VPRORVQ128,
 		ssa.OpAMD64VPRORVQ256,
 		ssa.OpAMD64VPRORVQ512,
-		ssa.OpAMD64VPACKSSDW128,
-		ssa.OpAMD64VPACKSSDW256,
-		ssa.OpAMD64VPACKSSDW512,
-		ssa.OpAMD64VPACKUSDW128,
-		ssa.OpAMD64VPACKUSDW256,
-		ssa.OpAMD64VPACKUSDW512,
 		ssa.OpAMD64VSCALEFPS128,
 		ssa.OpAMD64VSCALEFPS256,
 		ssa.OpAMD64VSCALEFPS512,
@@ -608,6 +608,12 @@
 		ssa.OpAMD64VPAVGWMasked128,
 		ssa.OpAMD64VPAVGWMasked256,
 		ssa.OpAMD64VPAVGWMasked512,
+		ssa.OpAMD64VPACKSSDWMasked256,
+		ssa.OpAMD64VPACKSSDWMasked512,
+		ssa.OpAMD64VPACKSSDWMasked128,
+		ssa.OpAMD64VPACKUSDWMasked256,
+		ssa.OpAMD64VPACKUSDWMasked512,
+		ssa.OpAMD64VPACKUSDWMasked128,
 		ssa.OpAMD64VDIVPSMasked128,
 		ssa.OpAMD64VDIVPSMasked256,
 		ssa.OpAMD64VDIVPSMasked512,
@@ -739,12 +745,6 @@
 		ssa.OpAMD64VPRORVQMasked128,
 		ssa.OpAMD64VPRORVQMasked256,
 		ssa.OpAMD64VPRORVQMasked512,
-		ssa.OpAMD64VPACKSSDWMasked256,
-		ssa.OpAMD64VPACKSSDWMasked512,
-		ssa.OpAMD64VPACKSSDWMasked128,
-		ssa.OpAMD64VPACKUSDWMasked256,
-		ssa.OpAMD64VPACKUSDWMasked512,
-		ssa.OpAMD64VPACKUSDWMasked128,
 		ssa.OpAMD64VSCALEFPSMasked128,
 		ssa.OpAMD64VSCALEFPSMasked256,
 		ssa.OpAMD64VSCALEFPSMasked512,
@@ -1425,6 +1425,12 @@
 		ssa.OpAMD64VPERMI2QMasked256,
 		ssa.OpAMD64VPERMI2PDMasked512,
 		ssa.OpAMD64VPERMI2QMasked512,
+		ssa.OpAMD64VPACKSSDWMasked256Merging,
+		ssa.OpAMD64VPACKSSDWMasked512Merging,
+		ssa.OpAMD64VPACKSSDWMasked128Merging,
+		ssa.OpAMD64VPACKUSDWMasked256Merging,
+		ssa.OpAMD64VPACKUSDWMasked512Merging,
+		ssa.OpAMD64VPACKUSDWMasked128Merging,
 		ssa.OpAMD64VDIVPSMasked128Merging,
 		ssa.OpAMD64VDIVPSMasked256Merging,
 		ssa.OpAMD64VDIVPSMasked512Merging,
@@ -1560,12 +1566,6 @@
 		ssa.OpAMD64VPRORVQMasked128Merging,
 		ssa.OpAMD64VPRORVQMasked256Merging,
 		ssa.OpAMD64VPRORVQMasked512Merging,
-		ssa.OpAMD64VPACKSSDWMasked256Merging,
-		ssa.OpAMD64VPACKSSDWMasked512Merging,
-		ssa.OpAMD64VPACKSSDWMasked128Merging,
-		ssa.OpAMD64VPACKUSDWMasked256Merging,
-		ssa.OpAMD64VPACKUSDWMasked512Merging,
-		ssa.OpAMD64VPACKUSDWMasked128Merging,
 		ssa.OpAMD64VSCALEFPSMasked128Merging,
 		ssa.OpAMD64VSCALEFPSMasked256Merging,
 		ssa.OpAMD64VSCALEFPSMasked512Merging,
@@ -1967,6 +1967,12 @@
 		ssa.OpAMD64VPHADDD256load,
 		ssa.OpAMD64VPHADDSW128load,
 		ssa.OpAMD64VPHADDSW256load,
+		ssa.OpAMD64VPACKSSDW128load,
+		ssa.OpAMD64VPACKSSDW256load,
+		ssa.OpAMD64VPACKSSDW512load,
+		ssa.OpAMD64VPACKUSDW128load,
+		ssa.OpAMD64VPACKUSDW256load,
+		ssa.OpAMD64VPACKUSDW512load,
 		ssa.OpAMD64VHSUBPS128load,
 		ssa.OpAMD64VHSUBPD128load,
 		ssa.OpAMD64VPHSUBW128load,
@@ -2131,12 +2137,6 @@
 		ssa.OpAMD64VPRORVQ128load,
 		ssa.OpAMD64VPRORVQ256load,
 		ssa.OpAMD64VPRORVQ512load,
-		ssa.OpAMD64VPACKSSDW128load,
-		ssa.OpAMD64VPACKSSDW256load,
-		ssa.OpAMD64VPACKSSDW512load,
-		ssa.OpAMD64VPACKUSDW128load,
-		ssa.OpAMD64VPACKUSDW256load,
-		ssa.OpAMD64VPACKUSDW512load,
 		ssa.OpAMD64VSCALEFPS128load,
 		ssa.OpAMD64VSCALEFPS256load,
 		ssa.OpAMD64VSCALEFPS512load,
@@ -2349,6 +2349,12 @@
 		ssa.OpAMD64VPAVGBMasked256load,
 		ssa.OpAMD64VPAVGWMasked128load,
 		ssa.OpAMD64VPAVGWMasked256load,
+		ssa.OpAMD64VPACKSSDWMasked256load,
+		ssa.OpAMD64VPACKSSDWMasked512load,
+		ssa.OpAMD64VPACKSSDWMasked128load,
+		ssa.OpAMD64VPACKUSDWMasked256load,
+		ssa.OpAMD64VPACKUSDWMasked512load,
+		ssa.OpAMD64VPACKUSDWMasked128load,
 		ssa.OpAMD64VDIVPSMasked128load,
 		ssa.OpAMD64VDIVPSMasked256load,
 		ssa.OpAMD64VDIVPSMasked512load,
@@ -2463,12 +2469,6 @@
 		ssa.OpAMD64VPRORVQMasked128load,
 		ssa.OpAMD64VPRORVQMasked256load,
 		ssa.OpAMD64VPRORVQMasked512load,
-		ssa.OpAMD64VPACKSSDWMasked256load,
-		ssa.OpAMD64VPACKSSDWMasked512load,
-		ssa.OpAMD64VPACKSSDWMasked128load,
-		ssa.OpAMD64VPACKUSDWMasked256load,
-		ssa.OpAMD64VPACKUSDWMasked512load,
-		ssa.OpAMD64VPACKUSDWMasked128load,
 		ssa.OpAMD64VSCALEFPSMasked128load,
 		ssa.OpAMD64VSCALEFPSMasked256load,
 		ssa.OpAMD64VSCALEFPSMasked512load,
@@ -3390,6 +3390,18 @@
 		ssa.OpAMD64VPERMI2PDMasked512load,
 		ssa.OpAMD64VPERMI2QMasked512,
 		ssa.OpAMD64VPERMI2QMasked512load,
+		ssa.OpAMD64VPACKSSDWMasked256,
+		ssa.OpAMD64VPACKSSDWMasked256load,
+		ssa.OpAMD64VPACKSSDWMasked512,
+		ssa.OpAMD64VPACKSSDWMasked512load,
+		ssa.OpAMD64VPACKSSDWMasked128,
+		ssa.OpAMD64VPACKSSDWMasked128load,
+		ssa.OpAMD64VPACKUSDWMasked256,
+		ssa.OpAMD64VPACKUSDWMasked256load,
+		ssa.OpAMD64VPACKUSDWMasked512,
+		ssa.OpAMD64VPACKUSDWMasked512load,
+		ssa.OpAMD64VPACKUSDWMasked128,
+		ssa.OpAMD64VPACKUSDWMasked128load,
 		ssa.OpAMD64VPALIGNRMasked256,
 		ssa.OpAMD64VPALIGNRMasked256load,
 		ssa.OpAMD64VPALIGNRMasked512,
@@ -3977,12 +3989,6 @@
 		ssa.OpAMD64VPMOVSQBMasked128_128,
 		ssa.OpAMD64VPMOVSQBMasked128_256,
 		ssa.OpAMD64VPMOVSQBMasked128_512,
-		ssa.OpAMD64VPACKSSDWMasked256,
-		ssa.OpAMD64VPACKSSDWMasked256load,
-		ssa.OpAMD64VPACKSSDWMasked512,
-		ssa.OpAMD64VPACKSSDWMasked512load,
-		ssa.OpAMD64VPACKSSDWMasked128,
-		ssa.OpAMD64VPACKSSDWMasked128load,
 		ssa.OpAMD64VPMOVSDWMasked128_128,
 		ssa.OpAMD64VPMOVSDWMasked128_256,
 		ssa.OpAMD64VPMOVSDWMasked256,
@@ -4001,12 +4007,6 @@
 		ssa.OpAMD64VPMOVUSQBMasked128_128,
 		ssa.OpAMD64VPMOVUSQBMasked128_256,
 		ssa.OpAMD64VPMOVUSQBMasked128_512,
-		ssa.OpAMD64VPACKUSDWMasked256,
-		ssa.OpAMD64VPACKUSDWMasked256load,
-		ssa.OpAMD64VPACKUSDWMasked512,
-		ssa.OpAMD64VPACKUSDWMasked512load,
-		ssa.OpAMD64VPACKUSDWMasked128,
-		ssa.OpAMD64VPACKUSDWMasked128load,
 		ssa.OpAMD64VPMOVUSDWMasked128_128,
 		ssa.OpAMD64VPMOVUSDWMasked128_256,
 		ssa.OpAMD64VPMOVUSDWMasked256,
diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
index 66f26b6..052344b 100644
--- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
+++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
@@ -226,6 +226,12 @@
 (ConcatPermute128ScalarsUint16x16 ...) => (VPERM2I128256 ...)
 (ConcatPermute128ScalarsUint32x8 ...) => (VPERM2I128256 ...)
 (ConcatPermute128ScalarsUint64x4 ...) => (VPERM2I128256 ...)
+(ConcatSaturateToInt16Int32x4 ...) => (VPACKSSDW128 ...)
+(ConcatSaturateToInt16GroupedInt32x8 ...) => (VPACKSSDW256 ...)
+(ConcatSaturateToInt16GroupedInt32x16 ...) => (VPACKSSDW512 ...)
+(ConcatSaturateToUint16Int32x4 ...) => (VPACKUSDW128 ...)
+(ConcatSaturateToUint16GroupedInt32x8 ...) => (VPACKUSDW256 ...)
+(ConcatSaturateToUint16GroupedInt32x16 ...) => (VPACKUSDW512 ...)
 (ConcatShiftBytesRightUint8x16 ...) => (VPALIGNR128 ...)
 (ConcatShiftBytesRightGroupedUint8x32 ...) => (VPALIGNR256 ...)
 (ConcatShiftBytesRightGroupedUint8x64 ...) => (VPALIGNR512 ...)
@@ -895,9 +901,6 @@
 (SaturateToInt16Int64x2 ...) => (VPMOVSQW128_128 ...)
 (SaturateToInt16Int64x4 ...) => (VPMOVSQW128_256 ...)
 (SaturateToInt16Int64x8 ...) => (VPMOVSQW128_512 ...)
-(SaturateToInt16ConcatInt32x4 ...) => (VPACKSSDW128 ...)
-(SaturateToInt16ConcatGroupedInt32x8 ...) => (VPACKSSDW256 ...)
-(SaturateToInt16ConcatGroupedInt32x16 ...) => (VPACKSSDW512 ...)
 (SaturateToInt32Int64x2 ...) => (VPMOVSQD128_128 ...)
 (SaturateToInt32Int64x4 ...) => (VPMOVSQD128_256 ...)
 (SaturateToInt32Int64x8 ...) => (VPMOVSQD256 ...)
@@ -916,9 +919,6 @@
 (SaturateToUint16Uint64x2 ...) => (VPMOVUSQW128_128 ...)
 (SaturateToUint16Uint64x4 ...) => (VPMOVUSQW128_256 ...)
 (SaturateToUint16Uint64x8 ...) => (VPMOVUSQW128_512 ...)
-(SaturateToUint16ConcatInt32x4 ...) => (VPACKUSDW128 ...)
-(SaturateToUint16ConcatGroupedInt32x8 ...) => (VPACKUSDW256 ...)
-(SaturateToUint16ConcatGroupedInt32x16 ...) => (VPACKUSDW512 ...)
 (SaturateToUint32Uint64x2 ...) => (VPMOVUSQD128_128 ...)
 (SaturateToUint32Uint64x4 ...) => (VPMOVUSQD128_256 ...)
 (SaturateToUint32Uint64x8 ...) => (VPMOVUSQD256 ...)
@@ -1556,6 +1556,12 @@
 (VMOVDQU64Masked256 (VPERMI2Q256 x y z) mask) => (VPERMI2QMasked256 x y z mask)
 (VMOVDQU64Masked512 (VPERMI2PD512 x y z) mask) => (VPERMI2PDMasked512 x y z mask)
 (VMOVDQU64Masked512 (VPERMI2Q512 x y z) mask) => (VPERMI2QMasked512 x y z mask)
+(VMOVDQU32Masked256 (VPACKSSDW256 x y) mask) => (VPACKSSDWMasked256 x y mask)
+(VMOVDQU32Masked512 (VPACKSSDW512 x y) mask) => (VPACKSSDWMasked512 x y mask)
+(VMOVDQU32Masked128 (VPACKSSDW128 x y) mask) => (VPACKSSDWMasked128 x y mask)
+(VMOVDQU32Masked256 (VPACKUSDW256 x y) mask) => (VPACKUSDWMasked256 x y mask)
+(VMOVDQU32Masked512 (VPACKUSDW512 x y) mask) => (VPACKUSDWMasked512 x y mask)
+(VMOVDQU32Masked128 (VPACKUSDW128 x y) mask) => (VPACKUSDWMasked128 x y mask)
 (VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) => (VPALIGNRMasked256 [a] x y mask)
 (VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) => (VPALIGNRMasked512 [a] x y mask)
 (VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) => (VPALIGNRMasked128 [a] x y mask)
@@ -1842,9 +1848,6 @@
 (VMOVDQU64Masked128 (VPMOVSQB128_128 x) mask) => (VPMOVSQBMasked128_128 x mask)
 (VMOVDQU64Masked256 (VPMOVSQB128_256 x) mask) => (VPMOVSQBMasked128_256 x mask)
 (VMOVDQU64Masked512 (VPMOVSQB128_512 x) mask) => (VPMOVSQBMasked128_512 x mask)
-(VMOVDQU32Masked256 (VPACKSSDW256 x y) mask) => (VPACKSSDWMasked256 x y mask)
-(VMOVDQU32Masked512 (VPACKSSDW512 x y) mask) => (VPACKSSDWMasked512 x y mask)
-(VMOVDQU32Masked128 (VPACKSSDW128 x y) mask) => (VPACKSSDWMasked128 x y mask)
 (VMOVDQU32Masked128 (VPMOVSDW128_128 x) mask) => (VPMOVSDWMasked128_128 x mask)
 (VMOVDQU32Masked256 (VPMOVSDW128_256 x) mask) => (VPMOVSDWMasked128_256 x mask)
 (VMOVDQU32Masked256 (VPMOVSDW256 x) mask) => (VPMOVSDWMasked256 x mask)
@@ -1863,9 +1866,6 @@
 (VMOVDQU64Masked128 (VPMOVUSQB128_128 x) mask) => (VPMOVUSQBMasked128_128 x mask)
 (VMOVDQU64Masked256 (VPMOVUSQB128_256 x) mask) => (VPMOVUSQBMasked128_256 x mask)
 (VMOVDQU64Masked512 (VPMOVUSQB128_512 x) mask) => (VPMOVUSQBMasked128_512 x mask)
-(VMOVDQU32Masked256 (VPACKUSDW256 x y) mask) => (VPACKUSDWMasked256 x y mask)
-(VMOVDQU32Masked512 (VPACKUSDW512 x y) mask) => (VPACKUSDWMasked512 x y mask)
-(VMOVDQU32Masked128 (VPACKUSDW128 x y) mask) => (VPACKUSDWMasked128 x y mask)
 (VMOVDQU32Masked128 (VPMOVUSDW128_128 x) mask) => (VPMOVUSDWMasked128_128 x mask)
 (VMOVDQU32Masked256 (VPMOVUSDW128_256 x) mask) => (VPMOVUSDWMasked128_256 x mask)
 (VMOVDQU32Masked256 (VPMOVUSDW256 x) mask) => (VPMOVUSDWMasked256 x mask)
@@ -2733,6 +2733,18 @@
 (VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
 (VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
 (VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
+(VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW128load {sym} [off] x ptr mem)
+(VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW256load {sym} [off] x ptr mem)
+(VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW512load {sym} [off] x ptr mem)
+(VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked256load {sym} [off] x ptr mask mem)
+(VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked512load {sym} [off] x ptr mask mem)
+(VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked128load {sym} [off] x ptr mask mem)
+(VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW128load {sym} [off] x ptr mem)
+(VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW256load {sym} [off] x ptr mem)
+(VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW512load {sym} [off] x ptr mem)
+(VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked256load {sym} [off] x ptr mask mem)
+(VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked512load {sym} [off] x ptr mask mem)
+(VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked128load {sym} [off] x ptr mask mem)
 (VPALIGNR128 [c]  x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPALIGNR128load {sym} [makeValAndOff(int32(uint8(c)),off)]  x ptr mem)
 (VPALIGNR256 [c]  x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPALIGNR256load {sym} [makeValAndOff(int32(uint8(c)),off)]  x ptr mem)
 (VPALIGNRMasked256 [c]  x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPALIGNRMasked256load {sym} [makeValAndOff(int32(uint8(c)),off)]  x ptr mask mem)
@@ -3363,18 +3375,6 @@
 (VPRORVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked128load {sym} [off] x ptr mask mem)
 (VPRORVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked256load {sym} [off] x ptr mask mem)
 (VPRORVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked512load {sym} [off] x ptr mask mem)
-(VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW128load {sym} [off] x ptr mem)
-(VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW256load {sym} [off] x ptr mem)
-(VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW512load {sym} [off] x ptr mem)
-(VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked256load {sym} [off] x ptr mask mem)
-(VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked512load {sym} [off] x ptr mask mem)
-(VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked128load {sym} [off] x ptr mask mem)
-(VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW128load {sym} [off] x ptr mem)
-(VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW256load {sym} [off] x ptr mem)
-(VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW512load {sym} [off] x ptr mem)
-(VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked256load {sym} [off] x ptr mask mem)
-(VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked512load {sym} [off] x ptr mask mem)
-(VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked128load {sym} [off] x ptr mask mem)
 (VSCALEFPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS128load {sym} [off] x ptr mem)
 (VSCALEFPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS256load {sym} [off] x ptr mem)
 (VSCALEFPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS512load {sym} [off] x ptr mem)
diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
index 0314d0e..3b033cc 100644
--- a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
+++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
@@ -227,6 +227,12 @@
 		{name: "ConcatPermuteUint64x2", argLength: 3},                                   // ARCH:amd64
 		{name: "ConcatPermuteUint64x4", argLength: 3},                                   // ARCH:amd64
 		{name: "ConcatPermuteUint64x8", argLength: 3},                                   // ARCH:amd64
+		{name: "ConcatSaturateToInt16GroupedInt32x8", argLength: 2},                     // ARCH:amd64
+		{name: "ConcatSaturateToInt16GroupedInt32x16", argLength: 2},                    // ARCH:amd64
+		{name: "ConcatSaturateToInt16Int32x4", argLength: 2},                            // ARCH:amd64
+		{name: "ConcatSaturateToUint16GroupedInt32x8", argLength: 2},                    // ARCH:amd64
+		{name: "ConcatSaturateToUint16GroupedInt32x16", argLength: 2},                   // ARCH:amd64
+		{name: "ConcatSaturateToUint16Int32x4", argLength: 2},                           // ARCH:amd64
 		{name: "ConcatSubPairsFloat32x4", argLength: 2},                                 // ARCH:amd64
 		{name: "ConcatSubPairsFloat64x2", argLength: 2},                                 // ARCH:amd64
 		{name: "ConcatSubPairsGroupedFloat32x8", argLength: 2},                          // ARCH:amd64
@@ -965,9 +971,6 @@
 		{name: "SaturateToInt8Int64x2", argLength: 1},                                   // ARCH:amd64
 		{name: "SaturateToInt8Int64x4", argLength: 1},                                   // ARCH:amd64
 		{name: "SaturateToInt8Int64x8", argLength: 1},                                   // ARCH:amd64
-		{name: "SaturateToInt16ConcatGroupedInt32x8", argLength: 2},                     // ARCH:amd64
-		{name: "SaturateToInt16ConcatGroupedInt32x16", argLength: 2},                    // ARCH:amd64
-		{name: "SaturateToInt16ConcatInt32x4", argLength: 2},                            // ARCH:amd64
 		{name: "SaturateToInt16Int32x4", argLength: 1},                                  // ARCH:amd64,arm64
 		{name: "SaturateToInt16Int32x8", argLength: 1},                                  // ARCH:amd64
 		{name: "SaturateToInt16Int32x16", argLength: 1},                                 // ARCH:amd64
@@ -987,9 +990,6 @@
 		{name: "SaturateToUint8Uint64x2", argLength: 1},                                 // ARCH:amd64
 		{name: "SaturateToUint8Uint64x4", argLength: 1},                                 // ARCH:amd64
 		{name: "SaturateToUint8Uint64x8", argLength: 1},                                 // ARCH:amd64
-		{name: "SaturateToUint16ConcatGroupedInt32x8", argLength: 2},                    // ARCH:amd64
-		{name: "SaturateToUint16ConcatGroupedInt32x16", argLength: 2},                   // ARCH:amd64
-		{name: "SaturateToUint16ConcatInt32x4", argLength: 2},                           // ARCH:amd64
 		{name: "SaturateToUint16Int32x4", argLength: 1},                                 // ARCH:arm64
 		{name: "SaturateToUint16Uint32x4", argLength: 1},                                // ARCH:amd64,arm64
 		{name: "SaturateToUint16Uint32x8", argLength: 1},                                // ARCH:amd64
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 6b0b531..a82c026 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -7407,6 +7407,12 @@
 	OpConcatPermuteUint64x2
 	OpConcatPermuteUint64x4
 	OpConcatPermuteUint64x8
+	OpConcatSaturateToInt16GroupedInt32x8
+	OpConcatSaturateToInt16GroupedInt32x16
+	OpConcatSaturateToInt16Int32x4
+	OpConcatSaturateToUint16GroupedInt32x8
+	OpConcatSaturateToUint16GroupedInt32x16
+	OpConcatSaturateToUint16Int32x4
 	OpConcatSubPairsFloat32x4
 	OpConcatSubPairsFloat64x2
 	OpConcatSubPairsGroupedFloat32x8
@@ -8145,9 +8151,6 @@
 	OpSaturateToInt8Int64x2
 	OpSaturateToInt8Int64x4
 	OpSaturateToInt8Int64x8
-	OpSaturateToInt16ConcatGroupedInt32x8
-	OpSaturateToInt16ConcatGroupedInt32x16
-	OpSaturateToInt16ConcatInt32x4
 	OpSaturateToInt16Int32x4
 	OpSaturateToInt16Int32x8
 	OpSaturateToInt16Int32x16
@@ -8167,9 +8170,6 @@
 	OpSaturateToUint8Uint64x2
 	OpSaturateToUint8Uint64x4
 	OpSaturateToUint8Uint64x8
-	OpSaturateToUint16ConcatGroupedInt32x8
-	OpSaturateToUint16ConcatGroupedInt32x16
-	OpSaturateToUint16ConcatInt32x4
 	OpSaturateToUint16Int32x4
 	OpSaturateToUint16Uint32x4
 	OpSaturateToUint16Uint32x8
@@ -108075,6 +108075,36 @@
 		generic: true,
 	},
 	{
+		name:    "ConcatSaturateToInt16GroupedInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ConcatSaturateToInt16GroupedInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ConcatSaturateToInt16Int32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ConcatSaturateToUint16GroupedInt32x8",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ConcatSaturateToUint16GroupedInt32x16",
+		argLen:  2,
+		generic: true,
+	},
+	{
+		name:    "ConcatSaturateToUint16Int32x4",
+		argLen:  2,
+		generic: true,
+	},
+	{
 		name:    "ConcatSubPairsFloat32x4",
 		argLen:  2,
 		generic: true,
@@ -111943,21 +111973,6 @@
 		generic: true,
 	},
 	{
-		name:    "SaturateToInt16ConcatGroupedInt32x8",
-		argLen:  2,
-		generic: true,
-	},
-	{
-		name:    "SaturateToInt16ConcatGroupedInt32x16",
-		argLen:  2,
-		generic: true,
-	},
-	{
-		name:    "SaturateToInt16ConcatInt32x4",
-		argLen:  2,
-		generic: true,
-	},
-	{
 		name:    "SaturateToInt16Int32x4",
 		argLen:  1,
 		generic: true,
@@ -112053,21 +112068,6 @@
 		generic: true,
 	},
 	{
-		name:    "SaturateToUint16ConcatGroupedInt32x8",
-		argLen:  2,
-		generic: true,
-	},
-	{
-		name:    "SaturateToUint16ConcatGroupedInt32x16",
-		argLen:  2,
-		generic: true,
-	},
-	{
-		name:    "SaturateToUint16ConcatInt32x4",
-		argLen:  2,
-		generic: true,
-	},
-	{
 		name:    "SaturateToUint16Int32x4",
 		argLen:  1,
 		generic: true,
diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index 38e0e92..4e23cf8 100644
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -3780,6 +3780,24 @@
 	case OpConcatPermuteUint8x64:
 		v.Op = OpAMD64VPERMI2B512
 		return true
+	case OpConcatSaturateToInt16GroupedInt32x16:
+		v.Op = OpAMD64VPACKSSDW512
+		return true
+	case OpConcatSaturateToInt16GroupedInt32x8:
+		v.Op = OpAMD64VPACKSSDW256
+		return true
+	case OpConcatSaturateToInt16Int32x4:
+		v.Op = OpAMD64VPACKSSDW128
+		return true
+	case OpConcatSaturateToUint16GroupedInt32x16:
+		v.Op = OpAMD64VPACKUSDW512
+		return true
+	case OpConcatSaturateToUint16GroupedInt32x8:
+		v.Op = OpAMD64VPACKUSDW256
+		return true
+	case OpConcatSaturateToUint16Int32x4:
+		v.Op = OpAMD64VPACKUSDW128
+		return true
 	case OpConcatShiftBytesRightGroupedUint8x32:
 		v.Op = OpAMD64VPALIGNR256
 		return true
@@ -6058,15 +6076,6 @@
 	case OpSHA256TwoRoundsUint32x4:
 		v.Op = OpAMD64SHA256RNDS2128
 		return true
-	case OpSaturateToInt16ConcatGroupedInt32x16:
-		v.Op = OpAMD64VPACKSSDW512
-		return true
-	case OpSaturateToInt16ConcatGroupedInt32x8:
-		v.Op = OpAMD64VPACKSSDW256
-		return true
-	case OpSaturateToInt16ConcatInt32x4:
-		v.Op = OpAMD64VPACKSSDW128
-		return true
 	case OpSaturateToInt16Int32x16:
 		v.Op = OpAMD64VPMOVSDW256
 		return true
@@ -6121,15 +6130,6 @@
 	case OpSaturateToInt8Int64x8:
 		v.Op = OpAMD64VPMOVSQB128_512
 		return true
-	case OpSaturateToUint16ConcatGroupedInt32x16:
-		v.Op = OpAMD64VPACKUSDW512
-		return true
-	case OpSaturateToUint16ConcatGroupedInt32x8:
-		v.Op = OpAMD64VPACKUSDW256
-		return true
-	case OpSaturateToUint16ConcatInt32x4:
-		v.Op = OpAMD64VPACKUSDW128
-		return true
 	case OpSaturateToUint16Uint32x16:
 		v.Op = OpAMD64VPMOVUSDW256
 		return true
@@ -50025,6 +50025,32 @@
 		v.AddArg4(x, y, z, mask)
 		return true
 	}
+	// match: (VMOVDQU32Masked128 (VPACKSSDW128 x y) mask)
+	// result: (VPACKSSDWMasked128 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKSSDW128 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKSSDWMasked128)
+		v.AddArg3(x, y, mask)
+		return true
+	}
+	// match: (VMOVDQU32Masked128 (VPACKUSDW128 x y) mask)
+	// result: (VPACKUSDWMasked128 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKUSDW128 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKUSDWMasked128)
+		v.AddArg3(x, y, mask)
+		return true
+	}
 	// match: (VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask)
 	// result: (VCVTDQ2PSMasked128 x mask)
 	for {
@@ -50346,19 +50372,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked128 (VPACKSSDW128 x y) mask)
-	// result: (VPACKSSDWMasked128 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKSSDW128 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKSSDWMasked128)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked128 (VPMOVSDW128_128 x) mask)
 	// result: (VPMOVSDWMasked128_128 x mask)
 	for {
@@ -50383,19 +50396,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked128 (VPACKUSDW128 x y) mask)
-	// result: (VPACKUSDWMasked128 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKUSDW128 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKUSDWMasked128)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked128 (VPMOVUSDW128_128 x) mask)
 	// result: (VPMOVUSDWMasked128_128 x mask)
 	for {
@@ -50774,6 +50774,32 @@
 		v.AddArg4(x, y, z, mask)
 		return true
 	}
+	// match: (VMOVDQU32Masked256 (VPACKSSDW256 x y) mask)
+	// result: (VPACKSSDWMasked256 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKSSDW256 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKSSDWMasked256)
+		v.AddArg3(x, y, mask)
+		return true
+	}
+	// match: (VMOVDQU32Masked256 (VPACKUSDW256 x y) mask)
+	// result: (VPACKUSDWMasked256 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKUSDW256 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKUSDWMasked256)
+		v.AddArg3(x, y, mask)
+		return true
+	}
 	// match: (VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask)
 	// result: (VCVTDQ2PSMasked256 x mask)
 	for {
@@ -51181,19 +51207,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked256 (VPACKSSDW256 x y) mask)
-	// result: (VPACKSSDWMasked256 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKSSDW256 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKSSDWMasked256)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked256 (VPMOVSDW128_256 x) mask)
 	// result: (VPMOVSDWMasked128_256 x mask)
 	for {
@@ -51230,19 +51243,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked256 (VPACKUSDW256 x y) mask)
-	// result: (VPACKUSDWMasked256 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKUSDW256 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKUSDWMasked256)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked256 (VPMOVUSDW128_256 x) mask)
 	// result: (VPMOVUSDWMasked128_256 x mask)
 	for {
@@ -51671,6 +51671,32 @@
 		v.AddArg4(x, y, z, mask)
 		return true
 	}
+	// match: (VMOVDQU32Masked512 (VPACKSSDW512 x y) mask)
+	// result: (VPACKSSDWMasked512 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKSSDW512 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKSSDWMasked512)
+		v.AddArg3(x, y, mask)
+		return true
+	}
+	// match: (VMOVDQU32Masked512 (VPACKUSDW512 x y) mask)
+	// result: (VPACKUSDWMasked512 x y mask)
+	for {
+		if v_0.Op != OpAMD64VPACKUSDW512 {
+			break
+		}
+		y := v_0.Args[1]
+		x := v_0.Args[0]
+		mask := v_1
+		v.reset(OpAMD64VPACKUSDWMasked512)
+		v.AddArg3(x, y, mask)
+		return true
+	}
 	// match: (VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask)
 	// result: (VCVTDQ2PSMasked512 x mask)
 	for {
@@ -52115,19 +52141,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked512 (VPACKSSDW512 x y) mask)
-	// result: (VPACKSSDWMasked512 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKSSDW512 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKSSDWMasked512)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked512 (VPMOVUSDB128_512 x) mask)
 	// result: (VPMOVUSDBMasked128_512 x mask)
 	for {
@@ -52140,19 +52153,6 @@
 		v.AddArg2(x, mask)
 		return true
 	}
-	// match: (VMOVDQU32Masked512 (VPACKUSDW512 x y) mask)
-	// result: (VPACKUSDWMasked512 x y mask)
-	for {
-		if v_0.Op != OpAMD64VPACKUSDW512 {
-			break
-		}
-		y := v_0.Args[1]
-		x := v_0.Args[0]
-		mask := v_1
-		v.reset(OpAMD64VPACKUSDWMasked512)
-		v.AddArg3(x, y, mask)
-		return true
-	}
 	// match: (VMOVDQU32Masked512 (VSCALEFPS512 x y) mask)
 	// result: (VSCALEFPSMasked512 x y mask)
 	for {
diff --git a/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
index 16da09b..cca60bc 100644
--- a/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
+++ b/src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
@@ -236,6 +236,12 @@
 	addF(simdPackage, "Uint16x16.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint16x16, types.TypeVec256, 0), sys.AMD64)
 	addF(simdPackage, "Uint32x8.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint32x8, types.TypeVec256, 0), sys.AMD64)
 	addF(simdPackage, "Uint64x4.ConcatPermute128Scalars", opLen2Imm8_II(ssa.OpConcatPermute128ScalarsUint64x4, types.TypeVec256, 0), sys.AMD64)
+	addF(simdPackage, "Int32x4.ConcatSaturateToInt16", opLen2(ssa.OpConcatSaturateToInt16Int32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ConcatSaturateToInt16Grouped", opLen2(ssa.OpConcatSaturateToInt16GroupedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ConcatSaturateToInt16Grouped", opLen2(ssa.OpConcatSaturateToInt16GroupedInt32x16, types.TypeVec512), sys.AMD64)
+	addF(simdPackage, "Int32x4.ConcatSaturateToUint16", opLen2(ssa.OpConcatSaturateToUint16Int32x4, types.TypeVec128), sys.AMD64)
+	addF(simdPackage, "Int32x8.ConcatSaturateToUint16Grouped", opLen2(ssa.OpConcatSaturateToUint16GroupedInt32x8, types.TypeVec256), sys.AMD64)
+	addF(simdPackage, "Int32x16.ConcatSaturateToUint16Grouped", opLen2(ssa.OpConcatSaturateToUint16GroupedInt32x16, types.TypeVec512), sys.AMD64)
 	addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0), sys.AMD64)
 	addF(simdPackage, "Uint8x32.ConcatShiftBytesRightGrouped", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightGroupedUint8x32, types.TypeVec256, 0), sys.AMD64)
 	addF(simdPackage, "Uint8x64.ConcatShiftBytesRightGrouped", opLen2Imm8_2I(ssa.OpConcatShiftBytesRightGroupedUint8x64, types.TypeVec512, 0), sys.AMD64)
@@ -905,9 +911,6 @@
 	addF(simdPackage, "Int64x2.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x2, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Int64x4.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x4, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Int64x8.SaturateToInt16", opLen1(ssa.OpSaturateToInt16Int64x8, types.TypeVec128), sys.AMD64)
-	addF(simdPackage, "Int32x4.SaturateToInt16Concat", opLen2(ssa.OpSaturateToInt16ConcatInt32x4, types.TypeVec128), sys.AMD64)
-	addF(simdPackage, "Int32x8.SaturateToInt16ConcatGrouped", opLen2(ssa.OpSaturateToInt16ConcatGroupedInt32x8, types.TypeVec256), sys.AMD64)
-	addF(simdPackage, "Int32x16.SaturateToInt16ConcatGrouped", opLen2(ssa.OpSaturateToInt16ConcatGroupedInt32x16, types.TypeVec512), sys.AMD64)
 	addF(simdPackage, "Int64x2.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x2, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Int64x4.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x4, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Int64x8.SaturateToInt32", opLen1(ssa.OpSaturateToInt32Int64x8, types.TypeVec256), sys.AMD64)
@@ -926,9 +929,6 @@
 	addF(simdPackage, "Uint64x2.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x2, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Uint64x4.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x4, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Uint64x8.SaturateToUint16", opLen1(ssa.OpSaturateToUint16Uint64x8, types.TypeVec128), sys.AMD64)
-	addF(simdPackage, "Int32x4.SaturateToUint16Concat", opLen2(ssa.OpSaturateToUint16ConcatInt32x4, types.TypeVec128), sys.AMD64)
-	addF(simdPackage, "Int32x8.SaturateToUint16ConcatGrouped", opLen2(ssa.OpSaturateToUint16ConcatGroupedInt32x8, types.TypeVec256), sys.AMD64)
-	addF(simdPackage, "Int32x16.SaturateToUint16ConcatGrouped", opLen2(ssa.OpSaturateToUint16ConcatGroupedInt32x16, types.TypeVec512), sys.AMD64)
 	addF(simdPackage, "Uint64x2.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x2, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Uint64x4.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x4, types.TypeVec128), sys.AMD64)
 	addF(simdPackage, "Uint64x8.SaturateToUint32", opLen1(ssa.OpSaturateToUint32Uint64x8, types.TypeVec256), sys.AMD64)
diff --git a/src/simd/archsimd/_gen/simdgen/ops/Converts/categories.yaml b/src/simd/archsimd/_gen/simdgen/ops/Converts/categories.yaml
index c72815f..0ee08a8 100644
--- a/src/simd/archsimd/_gen/simdgen/ops/Converts/categories.yaml
+++ b/src/simd/archsimd/_gen/simdgen/ops/Converts/categories.yaml
@@ -69,7 +69,7 @@
   regexpTag: "convert"
   documentation: !string |-
     // NAME truncates element values to int16.
-- go: "SaturateToInt16(Concat(Grouped)?)?"
+- go: "(Concat)?SaturateToInt16(Grouped)?"
   commutative: false
   regexpTag: "convert"
   documentation: !string |-
@@ -114,7 +114,7 @@
   regexpTag: "convert"
   documentation: !string |-
     // NAME truncates element values to uint16.
-- go: "SaturateToUint16(Concat(Grouped)?)?"
+- go: "(Concat)?SaturateToUint16(Grouped)?"
   commutative: false
   regexpTag: "convert"
   documentation: !string |-
diff --git a/src/simd/archsimd/_gen/simdgen/ops/Converts/go_amd64.yaml b/src/simd/archsimd/_gen/simdgen/ops/Converts/go_amd64.yaml
index e6869b6..86de5cd 100644
--- a/src/simd/archsimd/_gen/simdgen/ops/Converts/go_amd64.yaml
+++ b/src/simd/archsimd/_gen/simdgen/ops/Converts/go_amd64.yaml
@@ -441,7 +441,7 @@
   out:
     - base: uint
 # Truncating saturated packed
-- go: SaturateToInt16Concat
+- go: ConcatSaturateToInt16
   regexpTag: "convert"
   asm: "VPACKSSDW"
   addDoc: &satDocConcat
@@ -454,7 +454,7 @@
   out:
     - base: int
       bits: 128
-- go: SaturateToInt16ConcatGrouped
+- go: ConcatSaturateToInt16Grouped
   regexpTag: "convert"
   asm: "VPACKSSDW"
   addDoc: &satDocConcatGrouped
@@ -468,7 +468,7 @@
   out:
     - base: int
       bits: 256|512
-- go: SaturateToUint16Concat
+- go: ConcatSaturateToUint16
   regexpTag: "convert"
   asm: "VPACKUSDW"
   addDoc: *satDocConcat
@@ -478,7 +478,7 @@
   out:
     - base: uint
       bits: 128
-- go: SaturateToUint16ConcatGrouped
+- go: ConcatSaturateToUint16Grouped
   regexpTag: "convert"
   asm: "VPACKUSDW"
   addDoc: *satDocConcatGrouped
diff --git a/src/simd/archsimd/internal/simd_test/simd_test.go b/src/simd/archsimd/internal/simd_test/simd_test.go
index e42fd22..c598d6b 100644
--- a/src/simd/archsimd/internal/simd_test/simd_test.go
+++ b/src/simd/archsimd/internal/simd_test/simd_test.go
@@ -1448,56 +1448,56 @@
 }
 
 func TestSaturateConcat(t *testing.T) {
-	// Int32x4.SaturateToInt16Concat
+	// Int32x4.ConcatSaturateToInt16
 	forSlicePair(t, int32s, 4, func(x, y []int32) bool {
 		a, b := archsimd.LoadInt32x4(x), archsimd.LoadInt32x4(y)
 		var out [8]int16
-		a.SaturateToInt16Concat(b).StoreArray(&out)
+		a.ConcatSaturateToInt16(b).StoreArray(&out)
 		want := convConcatSlice(x, y, satToInt16)
 		return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 	})
-	// Int32x4.SaturateToUint16Concat
+	// Int32x4.ConcatSaturateToUint16
 	forSlicePair(t, int32s, 4, func(x, y []int32) bool {
 		a, b := archsimd.LoadInt32x4(x), archsimd.LoadInt32x4(y)
 		var out [8]uint16
-		a.SaturateToUint16Concat(b).StoreArray(&out)
+		a.ConcatSaturateToUint16(b).StoreArray(&out)
 		want := convConcatSlice(x, y, satToUint16)
 		return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 	})
 
 	if archsimd.X86.AVX2() {
-		// Int32x8.SaturateToInt16ConcatGrouped
+		// Int32x8.ConcatSaturateToInt16Grouped
 		forSlicePair(t, int32s, 8, func(x, y []int32) bool {
 			a, b := archsimd.LoadInt32x8(x), archsimd.LoadInt32x8(y)
 			var out [16]int16
-			a.SaturateToInt16ConcatGrouped(b).StoreArray(&out)
+			a.ConcatSaturateToInt16Grouped(b).StoreArray(&out)
 			want := convConcatGroupedSlice(x, y, satToInt16)
 			return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 		})
-		// Int32x8.SaturateToUint16ConcatGrouped
+		// Int32x8.ConcatSaturateToUint16Grouped
 		forSlicePair(t, int32s, 8, func(x, y []int32) bool {
 			a, b := archsimd.LoadInt32x8(x), archsimd.LoadInt32x8(y)
 			var out [16]uint16
-			a.SaturateToUint16ConcatGrouped(b).StoreArray(&out)
+			a.ConcatSaturateToUint16Grouped(b).StoreArray(&out)
 			want := convConcatGroupedSlice(x, y, satToUint16)
 			return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 		})
 	}
 
 	if archsimd.X86.AVX512() {
-		// Int32x16.SaturateToInt16ConcatGrouped
+		// Int32x16.ConcatSaturateToInt16Grouped
 		forSlicePair(t, int32s, 16, func(x, y []int32) bool {
 			a, b := archsimd.LoadInt32x16(x), archsimd.LoadInt32x16(y)
 			var out [32]int16
-			a.SaturateToInt16ConcatGrouped(b).StoreArray(&out)
+			a.ConcatSaturateToInt16Grouped(b).StoreArray(&out)
 			want := convConcatGroupedSlice(x, y, satToInt16)
 			return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 		})
-		// Int32x16.SaturateToUint16ConcatGrouped
+		// Int32x16.ConcatSaturateToUint16Grouped
 		forSlicePair(t, int32s, 16, func(x, y []int32) bool {
 			a, b := archsimd.LoadInt32x16(x), archsimd.LoadInt32x16(y)
 			var out [32]uint16
-			a.SaturateToUint16ConcatGrouped(b).StoreArray(&out)
+			a.ConcatSaturateToUint16Grouped(b).StoreArray(&out)
 			want := convConcatGroupedSlice(x, y, satToUint16)
 			return checkSlicesLogInput(t, out[:], want, 0, func() { t.Logf("x=%v, y=%v", x, y) })
 		})
diff --git a/src/simd/archsimd/ops_amd64.go b/src/simd/archsimd/ops_amd64.go
index 71d7fb8..016789c 100644
--- a/src/simd/archsimd/ops_amd64.go
+++ b/src/simd/archsimd/ops_amd64.go
@@ -1565,6 +1565,60 @@
 // Asm: VPERM2I128, CPU Feature: AVX2
 func (x Uint64x4) ConcatPermute128Scalars(lo, hi uint8, y Uint64x4) Uint64x4
 
+/* ConcatSaturateToInt16 */
+
+// ConcatSaturateToInt16 converts element values to int16 with signed saturation.
+// The converted elements from x will be packed to the lower part of the result vector,
+// the converted elements from y will be packed to the upper part of the result vector.
+//
+// Asm: VPACKSSDW, CPU Feature: AVX
+func (x Int32x4) ConcatSaturateToInt16(y Int32x4) Int16x8
+
+/* ConcatSaturateToInt16Grouped */
+
+// ConcatSaturateToInt16Grouped converts element values to int16 with signed saturation.
+// With each 128-bit as a group:
+// The converted elements from x will be packed to the lower part of the group in the result vector,
+// the converted elements from y will be packed to the upper part of the group in the result vector.
+//
+// Asm: VPACKSSDW, CPU Feature: AVX2
+func (x Int32x8) ConcatSaturateToInt16Grouped(y Int32x8) Int16x16
+
+// ConcatSaturateToInt16Grouped converts element values to int16 with signed saturation.
+// With each 128-bit as a group:
+// The converted elements from x will be packed to the lower part of the group in the result vector,
+// the converted elements from y will be packed to the upper part of the group in the result vector.
+//
+// Asm: VPACKSSDW, CPU Feature: AVX512
+func (x Int32x16) ConcatSaturateToInt16Grouped(y Int32x16) Int16x32
+
+/* ConcatSaturateToUint16 */
+
+// ConcatSaturateToUint16 converts element values to uint16 with unsigned saturation.
+// The converted elements from x will be packed to the lower part of the result vector,
+// the converted elements from y will be packed to the upper part of the result vector.
+//
+// Asm: VPACKUSDW, CPU Feature: AVX
+func (x Int32x4) ConcatSaturateToUint16(y Int32x4) Uint16x8
+
+/* ConcatSaturateToUint16Grouped */
+
+// ConcatSaturateToUint16Grouped converts element values to uint16 with unsigned saturation.
+// With each 128-bit as a group:
+// The converted elements from x will be packed to the lower part of the group in the result vector,
+// the converted elements from y will be packed to the upper part of the group in the result vector.
+//
+// Asm: VPACKUSDW, CPU Feature: AVX2
+func (x Int32x8) ConcatSaturateToUint16Grouped(y Int32x8) Uint16x16
+
+// ConcatSaturateToUint16Grouped converts element values to uint16 with unsigned saturation.
+// With each 128-bit as a group:
+// The converted elements from x will be packed to the lower part of the group in the result vector,
+// the converted elements from y will be packed to the upper part of the group in the result vector.
+//
+// Asm: VPACKUSDW, CPU Feature: AVX512
+func (x Int32x16) ConcatSaturateToUint16Grouped(y Int32x16) Uint16x32
+
 /* ConcatShiftBytesRight */
 
 // ConcatShiftBytesRight concatenates x and y and shifts it right by shift bytes.
@@ -5481,33 +5535,6 @@
 // Asm: VPMOVSQW, CPU Feature: AVX512
 func (x Int64x8) SaturateToInt16() Int16x8
 
-/* SaturateToInt16Concat */
-
-// SaturateToInt16Concat converts element values to int16 with signed saturation.
-// The converted elements from x will be packed to the lower part of the result vector,
-// the converted elements from y will be packed to the upper part of the result vector.
-//
-// Asm: VPACKSSDW, CPU Feature: AVX
-func (x Int32x4) SaturateToInt16Concat(y Int32x4) Int16x8
-
-/* SaturateToInt16ConcatGrouped */
-
-// SaturateToInt16ConcatGrouped converts element values to int16 with signed saturation.
-// With each 128-bit as a group:
-// The converted elements from x will be packed to the lower part of the group in the result vector,
-// the converted elements from y will be packed to the upper part of the group in the result vector.
-//
-// Asm: VPACKSSDW, CPU Feature: AVX2
-func (x Int32x8) SaturateToInt16ConcatGrouped(y Int32x8) Int16x16
-
-// SaturateToInt16ConcatGrouped converts element values to int16 with signed saturation.
-// With each 128-bit as a group:
-// The converted elements from x will be packed to the lower part of the group in the result vector,
-// the converted elements from y will be packed to the upper part of the group in the result vector.
-//
-// Asm: VPACKSSDW, CPU Feature: AVX512
-func (x Int32x16) SaturateToInt16ConcatGrouped(y Int32x16) Int16x32
-
 /* SaturateToInt32 */
 
 // SaturateToInt32 converts element values to int32 with signed saturation.
@@ -5614,33 +5641,6 @@
 // Asm: VPMOVUSQW, CPU Feature: AVX512
 func (x Uint64x8) SaturateToUint16() Uint16x8
 
-/* SaturateToUint16Concat */
-
-// SaturateToUint16Concat converts element values to uint16 with unsigned saturation.
-// The converted elements from x will be packed to the lower part of the result vector,
-// the converted elements from y will be packed to the upper part of the result vector.
-//
-// Asm: VPACKUSDW, CPU Feature: AVX
-func (x Int32x4) SaturateToUint16Concat(y Int32x4) Uint16x8
-
-/* SaturateToUint16ConcatGrouped */
-
-// SaturateToUint16ConcatGrouped converts element values to uint16 with unsigned saturation.
-// With each 128-bit as a group:
-// The converted elements from x will be packed to the lower part of the group in the result vector,
-// the converted elements from y will be packed to the upper part of the group in the result vector.
-//
-// Asm: VPACKUSDW, CPU Feature: AVX2
-func (x Int32x8) SaturateToUint16ConcatGrouped(y Int32x8) Uint16x16
-
-// SaturateToUint16ConcatGrouped converts element values to uint16 with unsigned saturation.
-// With each 128-bit as a group:
-// The converted elements from x will be packed to the lower part of the group in the result vector,
-// the converted elements from y will be packed to the upper part of the group in the result vector.
-//
-// Asm: VPACKUSDW, CPU Feature: AVX512
-func (x Int32x16) SaturateToUint16ConcatGrouped(y Int32x16) Uint16x32
-
 /* SaturateToUint32 */
 
 // SaturateToUint32 converts element values to uint32 with unsigned saturation.

Change information

Files:

M src/cmd/compile/internal/amd64/simdssa.go
M src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
M src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
M src/cmd/compile/internal/ssa/opGen.go
M src/cmd/compile/internal/ssa/rewriteAMD64.go
M src/cmd/compile/internal/ssagen/simdAMD64intrinsics.go
M src/simd/archsimd/_gen/simdgen/ops/Converts/categories.yaml
M src/simd/archsimd/_gen/simdgen/ops/Converts/go_amd64.yaml
M src/simd/archsimd/internal/simd_test/simd_test.go
M src/simd/archsimd/ops_amd64.go

Change size: L

Delta: 10 files changed, 282 insertions(+), 282 deletions(-)

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[go/dev.simd] [dev.simd] simd, cmd/compile: SaturateToConcat -> ConcatSaturateTo

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