[go] simdgen: update for op pkg move
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Gopher Robot (Gerrit)
Aug 14, 2026, 11:18:34 PM (2 days ago) Aug 14
to Michael Matloob, goph...@pubsubhelper.golang.org, golang-...@googlegroups.com, Dmitri Shuralyov, Dmitri Shuralyov, golang...@luci-project-accounts.iam.gserviceaccount.com, Keith Randall, Michael Matloob, Cherry Mui, golang-co...@googlegroups.com
Gopher Robot submitted the change with unreviewed changes![]( "Open in Gerrit")
Unreviewed changes
9 is the latest approved patch-set.
The change was submitted with unreviewed changes in the following files:
```
The name of the file: src/simd/archsimd/_gen/tmplgen/main.go
Insertions: 1, Deletions: 0.
@@ -1402,6 +1402,7 @@
const (
phase0Start = iota
+ phase0Export
phase1Op
phase2Core
phase3Compile
```
```
The name of the file: src/simd/archsimd/_gen/simdgen/main.go
Insertions: 7, Deletions: 5.
@@ -143,15 +143,15 @@
var splitPhase = phase0Start
var (
+ title = identity
+
splitOpPkg = "cmd/compile/internal/ssa"
splitCorePath = "cmd/compile/internal/ssa"
splitCorePkg = "ssa"
splitCorePrefix = ""
- splitCoreTitle = identity
splitConvPrefix = ""
- splitConvTitle = identity
)
var splitFuncs = template.FuncMap{
@@ -159,7 +159,7 @@
"OpPkg": func() string { return path.Base(splitOpPkg) },
"CoreImport": func() string { return strconv.Quote(splitCorePath) },
"CorePkg": func() string { return splitCorePkg },
- "ConvName": func(name string) string { return splitConvPrefix + splitConvTitle(name) },
+ "ConvName": func(name string) string { return splitConvPrefix + title(name) },
}
func identity(s string) string { return s }
@@ -168,6 +168,7 @@
const (
phase0Start = iota
+ phase0Export
phase1Op
phase2Core
phase3Compile
@@ -177,6 +178,9 @@
)
func init() {
+ if splitPhase >= phase0Export {
+ title = simpleTitle
+ }
if splitPhase >= phase1Op {
splitOpPkg = "cmd/compile/internal/ssa/ssaop"
}
@@ -184,7 +188,6 @@
splitCorePath = "cmd/compile/internal/ssa/ssacore"
splitCorePkg = "ssacore"
splitCorePrefix = "ssacore."
- splitCoreTitle = simpleTitle
}
if splitPhase >= phase4CoreRename {
splitCorePath = "cmd/compile/internal/ssa"
@@ -193,7 +196,6 @@
}
if splitPhase >= phase5Conv {
splitConvPrefix = "ssa."
- splitConvTitle = simpleTitle
}
}
```
```
The name of the file: src/simd/archsimd/_gen/simdgen/gen_simdrules.go
Insertions: 5, Deletions: 5.
@@ -393,7 +393,7 @@
origArgs = after
}
immArg = "[c] "
- immArgCombineOff = " [" + splitCorePrefix + splitCoreTitle("makeValAndOff") + "(int32(uint8(c)),off)] "
+ immArgCombineOff = " [" + splitCorePrefix + title("makeValAndOff") + "(int32(uint8(c)),off)] "
}
memOpData.ArgsLoadAddr = immArg + origArgs + fmt.Sprintf("l:(VMOVDQUload%d {sym} [off] ptr mem)", *lastVreg.Bits)
// Remove the last vreg from the arg and change it to "ptr".
@@ -406,9 +406,9 @@
if gOp.MemFeaturesData != nil {
_, feat2 := getVbcstData(*gOp.MemFeaturesData)
knownFeatChecks := map[string]string{
- "AVX": "v.Block.CPUfeatures." + splitCoreTitle("hasFeature") + "(" + splitCorePrefix + "CPUavx)",
- "AVX2": "v.Block.CPUfeatures." + splitCoreTitle("hasFeature") + "(" + splitCorePrefix + "CPUavx2)",
- "AVX512": "v.Block.CPUfeatures." + splitCoreTitle("hasFeature") + "(" + splitCorePrefix + "CPUavx512)",
+ "AVX": "v.Block.CPUfeatures." + title("hasFeature") + "(" + splitCorePrefix + "CPUavx)",
+ "AVX2": "v.Block.CPUfeatures." + title("hasFeature") + "(" + splitCorePrefix + "CPUavx2)",
+ "AVX512": "v.Block.CPUfeatures." + title("hasFeature") + "(" + splitCorePrefix + "CPUavx512)",
}
memOpData.FeatCheck = knownFeatChecks[feat2]
memOpData.TplName = "vregMemFeatCheck"
@@ -438,7 +438,7 @@
noMaskName := machineOpName(NoMask, gOp)
ruleExisting, ok := maskedMergeOpts[noMaskName]
rule := fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.%s(%sCPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM <types.TypeMask> mask))\n",
- *maskElem.Bits, noMaskName, data.Args, splitCoreTitle("hasFeature"), splitCorePrefix, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes)
+ *maskElem.Bits, noMaskName, data.Args, title("hasFeature"), splitCorePrefix, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes)
if ok && ruleExisting != rule {
panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule))
} else {
```
```
The name of the file: src/simd/archsimd/_gen/wasmgen/main.go
Insertions: 1, Deletions: 0.
@@ -46,6 +46,7 @@
const (
phase0Start = iota
+ phase0Export
phase1Op
phase2Core
phase3Compile
```
Change information
Commit message:
src/simd/archsimd/_gen: prepare for ssa refactor
This change adds a phase variable in simdgen/tmplgen/wasmgen that
controls how the files are generated so that they can stay up to date
with the refactoring work that we do in upcoming CLs. We'll update
the behavior of the generator in those CLs by changing the value of the
variable.
Change-Id: I17a834793f48ffb330099ac5d74f4f4b6a6a6964
Reviewed-on: https://go-review.googlesource.com/c/go/+/810160
Reviewed-by: Keith Randall <k...@golang.org>
Reviewed-by: Dmitri Shuralyov <dmit...@google.com>
Reviewed-by: Michael Matloob <mat...@google.com>
Auto-Submit: Michael Matloob <mat...@golang.org>
LUCI-TryBot-Result: golang...@luci-project-accounts.iam.gserviceaccount.com <golang...@luci-project-accounts.iam.gserviceaccount.com>
Files:
- M src/simd/archsimd/_gen/simdgen/gen_simdIntrinsics.go
- M src/simd/archsimd/_gen/simdgen/gen_simdrules.go
- M src/simd/archsimd/_gen/simdgen/gen_simdssa.go
- M src/simd/archsimd/_gen/simdgen/gen_utility.go
- M src/simd/archsimd/_gen/simdgen/main.go
- M src/simd/archsimd/_gen/tmplgen/main.go
- M src/simd/archsimd/_gen/wasmgen/main.go
Change size: L
Delta: 7 files changed, 268 insertions(+), 92 deletions(-)
Branch: refs/heads/master
Submit Requirements:
Code-Review: +2 by Keith Randall, +1 by Dmitri Shuralyov, +1 by Michael Matloob
TryBots-Pass: LUCI-TryBot-Result+1 by golang...@luci-project-accounts.iam.gserviceaccount.com
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