Unreviewed changes
1 is the latest approved patch-set.
The change was submitted with unreviewed changes in the following files:
```
The name of the file: riscv64/riscv64asm/plan9x.go
Insertions: 10, Deletions: 6.
@@ -188,17 +188,21 @@
FNMSUB_D, FNMSUB_H, FNMSUB_Q, FNMSUB_S:
args[1], args[3] = args[3], args[1]
- case FMV_X_W, FMV_W_X:
+ case FMV_W_X:
+ if inst.Args[1].(Reg) == X0 {
+ args[1] = "$(0.0)"
+ }
+ fallthrough
+ case FMV_X_W:
op = "MOVF"
- if inst.Args[1].(Reg) == X0 {
- args[1] = "$(0.0)"
- }
- case FMV_X_D, FMV_D_X:
- op = "MOVD"
+ case FMV_D_X:
if inst.Args[1].(Reg) == X0 {
args[1] = "$(0.0)"
}
+ fallthrough
+ case FMV_X_D:
+ op = "MOVD"
case FSGNJ_S:
if inst.Args[2] == inst.Args[1] {
```
Change information
Commit message:
riscv64: fix and update decoding of MOVD and MOVF
Change https://go-review.googlesource.com/c/go/+/703216 enhances
MOVD and MOVF so that they can be used to initialise a floating
point register to 0.0 and also to copy the binary representations
of floating point values between integer and floating point registers.
We update the riscv64 plan9 disassembler to recognise these cases
and output the appropriate MOVD/MOVF instructions.
We also fix a bug in the plan9 decoder which results in the
arguments for the MOVD and MOVF instructions that represent loads
and stores being output in the wrong order.
Change-Id: I5c3561437f5a0c936767497de6e22c976ce17cff
Files:
- M riscv64/riscv64asm/plan9x.go
- M riscv64/riscv64asm/testdata/plan9cases.txt
Change size: S
Delta: 2 files changed, 28 insertions(+), 9 deletions(-)
Branch: refs/heads/master
Submit Requirements:
Code-Review: +2 by Meng Zhuo, +1 by Junyang Shao, +1 by Michael Knyszek, +2 by Joel Sing
TryBots-Pass: LUCI-TryBot-Result+1 by Go LUCI