I'm new to writing makefiles!
I want to do the following:
`make ARGS= "exec_file src_1 src_2 etc"'
I realize that $(ARGS) will contain _all_ the arguments. I need to
come up with a way to split out each argument to get to:
EXEC-FILE = exec_file
SRCS = src_1 src_2 src_3
I'm trying to create a "generic" makefile for a non-C compiler. Is
this possible? TIA...
--
Duke
Then why not simply do:
make EXEC-FILE=exec_file SRCS="src_1 src_2 src_3"
But if you really want to use your syntax you could also do:
EXEC-FILE= $(word 1, $(ARGS))
SRCS = $(wordlist 2, 999, $(ARGS))
> I'm trying to create a "generic" makefile for a non-C compiler. Is
> this possible? TIA...
Of course it is possible to do other things than compiling C code. Make
simply tries to create files when it finds that some other files are newer.
This creation of files could be done by running a C compiler, but it could
also be done with any other tool of your choice.
regards Henrik
--
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Ok! That's a more verbose way. Thanks!
> But if you really want to use your syntax you could also do:
>
> EXEC-FILE= $(word 1, $(ARGS))
> SRCS = $(wordlist 2, 999, $(ARGS))
I knew there should be a way to split out those args! :) Thanks -
again!
> > I'm trying to create a "generic" makefile for a non-C compiler. Is
> > this possible? TIA...
>
> Of course it is possible to do other things than compiling C code. Make
> simply tries to create files when it finds that some other files are newer.
> This creation of files could be done by running a C compiler, but it could
> also be done with any other tool of your choice.
I've been doing more Googling and reading, and indeed I see that
Makefiles
can be very flexible
Much obliged!
--
Duke