Fully Differential Folded Cascode Amplifier

[Jenelle Centeno]

Thisdocument summarizes the design of a fully differential operational amplifier and a second-order Butterworth filter using the designed op-amp. The op-amp was designed using a folded-cascode topology to meet specifications across temperature variations. Simulation results showed it met most specifications. A layout was created and tested, matching the schematic performance. A Butterworth biquad filter was also designed using the op-amp, with simulation results showing corner frequencies around the specified 22kHz point across temperatures.Read less

Shockingly simple question but for some reason I cannot get a configuration to work. I already designed a folded cascode op-amp and I can measure the slew rate using the Cadence function "SlewRate" and the differential output (vout_p - vout_n) with a differential input pulse, but this is for an open loop configuration with a capacitive load, like how you would expect to measure gain and phase margin. I got around 50V/us, but for my design this number seems suspiciously high. The answer is easy for single ended op-amps, as you can just use negative feedback, but I have not found a definitive answer anywhere for the commonly accepted configuration. Surely my brain is tired and I am missing something obvious, but I'd rather figure it out before bed.

The first thing to make sure of in order to apply a similar test you would use in a single ended configuration, is you need establish a common mode feedback and make sure the common mode at the output is fixed (usually half supply). When you are using single ended DC feedback it is working well because your feedback fixes the output to a known fixed value where the amplifier is operating in a linear region. Same applies with fully differential, but the operating point is fixed by the CMFB loop (even if the main loop is open!).

You can also use open loop, similar to what you do with single ended configurations. Your expected slew rate can be estimated using I=CL*SR, where CL is the load capacitance (no load would just be output node capacitance) and I is the bias current of the op amp, or just measure SR=dV/dT. Since it is likely an OTA, a resistance load is not necessary. However, you can add capacitive feedback with very large resistors in parallel to clamp the dc feedback, if you want to measure under a closed loop load.

For Gain and PM in open loop, as long as you have op pt. fixed by CMFB, you can justuse estimated load capacitance on each leg (like e.g. 1p) and measure the fully differential G/PM by subtracting both output AC signals and plotting differential G/PM.

Now I am designing single ended folded cascode amplifier in 0.13um technology. Supply voltage 1.2V. Input is NMOS. I am using 4 stack 2 branch cascode. upper 2 stacks are PMOS and lower is NMOS. My problem is gain is not increasing and unity gain bandwidth is very low. currently gain is 33dB and unity BW is 35MHz. Though I try to increase power but BW is not increasing. Any body gives some hints about that problem will be helpful for me.

The work done represents the overall structure and comparative analysis of folded cascode operational amplifier (op-amp) in fully differential configuration having PMOS and NMOS input stages with robust biasing and common mode feedback circuit under different process, voltage and temperature variations in 180nm technology with 1.8V power supply and 1pf load resulting in good optimization among the parameters such as gain, bandwidth, phase margin and power dissipation.

Afterwards i have built a differential amplifier which has common mode feedback(differential feedback), a current probe was connected like before on one of the feedback connections as shown bellow marked with red arrow.

However, by comparing with the classical way of measuring phase margin.

The STB shows me 41 degrees phase margin,where as in the classical view shown in the plot,at 0dN i have -182 phase which means 2 degree PM.

The only "classical" way I am aware of is that where you attempt to keep the loop closed during DC (to ensure that the operating point is found) and then open it during AC to measure the open loop gain at a particular point. That's usually achieved either using spectre's switch component (e.g the spt1switch), resistors which have a different AC resistance than DC resistance, or large inductors/capacitors. All of these approaches give the wrong answer because they do not load the circuit properly and can be very hard to implement using deeply embedded loops - stb analysis ensures that the loop stays closed at all points and measures the loop gain (it's like Middlebrook's method but with improvements which avoid the direction problems that Middlebrook's method has).

Anyway, I can't see what "differential" feedback you're talking about here (your schematics are rather badly drawn which makes them hard to follow too). You can measure differential and common-mode stability using the diffstbprobe component from analogLib and then the stb analysis can show you the stability for the differential or common-mode loop gain, but I'm not sure that's what you're asking.

This is just because you have the inputs of the diffstbprobe connected to the inputs of the transistors (gates) so the schematic checker (which is quite a simple tool) thinking that nothing is driving the nets. I don't think these should matter because the direction of the probes don't really matter, but I think the probe would make more sense if flipped from left to right so that the outputs connect to the gates and that would also eliminate the warnings from the schematic checker.

Hello Andrew, i have rotate the probe like you said and it gave me the same error i had on the last problem where i didnt have any feedback loop.(which was solved when i connected the loop feedback,although it had a "forced" voltage supllies connected directly.)

To be honest, I've not got the time (as I've said repeatedly) to keep debugging your setup and circuit; you need to find some assistance within your university, or contact customer support as looking at this from pictures alone is very time consuming.

You have really not provided sufficient information to provide a complete answer to your stability issue. However, I believe I know the root cause of your issue without any detailed information as both Andrew and I have corrected so many of your prior issues.

You are not showing the DC operating points of any of your transistors not how you are generating the cascode bias voltages Vb2 or Vb3. I highly suspect that your bias conditions are not optimal for your folded cascode. The optimal biasing of folded cascode amplifiers is non-trivial. As a result of non-optimal biasing, I suspect your loop gain is not sufficient for any reasonable gain. This is my guess as to why your stability result suggests the differential gain is less than 0 dB.

I, personally, believe I mentioned to you that as part of the learning process you need to study and think about your results before posting an item to request others to solve it for you. Without doing this, if you end up working in the field, you will never be able to solve a problem in your own. Now is the time to start - not after you find a position in a company.

This op amp is a 3 stage architecture. The bias voltages are generated using a high swing cascode configuration shown in the bias generator section. I arbitrarily set these bias currents to 5u. This current can be scaled up or down depending on the size of the subsequent mirror transistors. the currents used in the various stages should depend on what bandwidth and gain constraints are imposed on the design. Since I am using this op amp for a low frequency application, I did not give too much importance to BW. However, I believe a folded cascode inherently has a higher BW than a normal single transistor design because the pole at the output node will see a reduced capacitance. In addition, a higher current through the folded cascode will yield a higher bandwidth due to reduced output resistance. I will update with proper reasoning and quantitative analysis of this feature.

The input stage consists of a basic PMOS differential input tied to the folded cascode structure. The NMOS current source of the folded cascode should be able to sink at least the same amount of current as the differential pair current source. The current source of the folded cascode should also have a high rout to improve its operation as a current source. The rout of the top two PMOS devices should be large to produce a high gain but should also be able to maintain the given current with an acceptable Vds.

The CMV of the folded cascode is actually set by the mechanisms of the final CS stage. The last stage is a simple CS NMOS amplifier loaded with an active PMOS current source. The CMV of the output is sensed through two resistors and passed to a rudimentary op amp which controls the PMOS current source of the folded cascode. This will adjust the voltage at the output to ensure that the subsequent CS stage converges to a proper CMV. This voltage turned out to be roughly .65V, or half the supply voltage of 1.3V. Thus, the output signal will have a CMV of .65V nominally.

It must be noted that, since this op amp has a fully differential output, I am not quite sure if the same Middlebrook techniques apply for open loop gain calculations. There is a paper regarding this subject which I will read and then I will update this post if there exists a different configuration for this.

UPDATE: The Middlebrook method is not needed for gain and phase margin analysis. A simple AC simulation will yield proper results, but care must be taken to ensure that the output is differential and not single ended.

The goal of this project is to design a fully differential folded cascode OTA with a common mode feedback network. this circuit can be used as a building block in larger systems such as active filters and data converters.

The Common-mode feedback network is used to stabilize the output common-mode voltage without affecting the differential mode operation. The CMFB loop senses the CM output level and compares it with the specified reference voltage value, then adjusts the bias voltage of the amplifier to correct the error and force the output voltage to the specified reference value.

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