Hello Everyone,
A new Genesis2 release is now available (default at Stanford; other locations send me an email to get the tarball). Here is what's new:
Expending to TCL and High Level Synthesis (beta)
There is more than just verilog to be generated. Whether it is tcl scripts for the back end, or C code for high level synthesis (HLS). So this version is the first to support .cp and .tckp files. I am still trying to figure out what would be the right way to handle those types. Whether they should go to separate folders, file lists, etc. But I have a good feeling that it might lead somewhere interesting with some help from new friends at UCLA ;-)
Executable Configuration
In the previous release, we added the ability to specify a script that uses a 'configure' function to set parameters. Here we add a bunch of capability due to popular demand. In particular, we give you the ability to define your own package, say my_chip_config.pm that defines high level functions, and then internally translate those to configure the internals of the design. Read more about it in Genesis2#Config_Libraries. Functions available include 'exists_configuration', 'get_configuration', 'remove_configuration', 'get_top_name', 'get_synthtop_path', and the lovely 'print_configuration' (see details at Genesis2#Basic_Config_Files)
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Pretty Print
In the spirit of "creeping excellence": remember that every parameter you define, leaves a verilog comment with its assigned value? remember how long that comment is for compound data structures? Well, no more. From now on it is short, beautiful and concise. Seriously, try it. It's beautiful.
More Errors Caught, Nicer Error Messages
Again, in the spirit of "creeping excellence": taking your feedback, we try to improve the types of errors we catch (thanks Glen), and the messages we produce.
Log Your Command Line, Genesis2 Version and More into Genesis.log
Every message genesis produces to screen is now also captures genesis.log. More over, your complete command line and the Genesis2 version information is also captured there. You can change the name of the log file if you want with the '-log myfile.log' flag.
Support for Gate Level Simulation
We started with genesis creating the genesis_vlog.vf file list that all tools down stream need. We made it list the files in reverse DFS order so that down stream tools don't need to work too hard (those whiners :-) We then added a genesis_vlog.synth.vf file list, with only the for-synthesis files to make it easy for the backend.
But what if we want to run gate level simulation? Today we also add the genesis_vlog.verif.vf list that contains all the files needed for validation, but without the design itself as that file would be the netlist coming of the design compiler.
More stuff to come soon. Stay tuned. Meanwhile, your feedback is always welcome!
Best,
Ofer.