GATE-2000 CO doubt

[srikanta s]

Comparing the time Ti taken for a single instruction on a pipelined CPU with time T2 taken

on a non-pipelined but identical CPU, we can say that

(a) Ti = T2

(b) Ti > T2

(c) Ti <T2

(d) Ti is T2 plus the time taken for one instruction fetch cycle

[Ravi]

For a single operation(not many,it is important to note this) it is same whether in pipelined or not..but when it comes to pipelined, there will be a small delay added because of the buffers between the stages..so T1 will be more than T2..

[ASHISH SONI]

I am not satisfied with your ans sir because the pipelinig is used
only to work effiently the all stages but in above question they say
only single instruction and accordin to sagar sir the first
instuction is goes in non-pipeline fashion rest of instruction goes
pipeline fashion that why we are using (k+n-1)*t
where k=stages ,t=time
but we take n-1 because first insturction goes non pipeline fashion

and more over they not mentioned any where about first intruction so
both will take same time
so ans will be (i)

[Ravi]

Please try to understand that even pipelined or nonpipelined, every instruction needs all stages and in pipeline, it gives an illusion that one instruction take one cycle.. :)

[ASHISH SONI]

ans may be Ti<=T2 because if we take set of instruction and taking
single instruction from them then in non pipeline it will executed
after previous & in pipeline they will only wait to free the first
stage if first will free they will start to execute the instruction